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STM32WLE4JCU6TR Datenblatt(PDF) 121 Page - STMicroelectronics

Teilenummer STM32WLE4JCU6TR
Bauteilbeschribung  Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
PDF  145 Pages
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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STM32WLE4JCU6TR Datenblatt(HTML) 121 Page - STMicroelectronics

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DS13105 Rev 8
121/145
STM32WLE5/E4xx
Electrical characteristics
133
Figure 24. VREFOUT_TEMP when VRS = 0
Iline_reg
Line regulation
2.8 V ≤ VDDA ≤ 3.6 V
Normal
mode
-
-
2000
ppm
/V
Iload_reg
Load regulation
500 μA ≤ Iload ≤ 4 mA
Normal
mode
-50
500
ppm
/mA
Tcoeff
Temperature
coefficient
-40 °C < TJ < +105 °C
-
-
±[Tcoeff _ vrefint
+ 50]
ppm
/°C
0 °C < TJ < +50 °C
-
-
±[Tcoeff_vrefint
+ 50]
PSRR
Power supply
rejection
DC
40
55
-
dB
100 kHz
25
40
-
tSTART
Startup time
CL = 0.5 µF(3)
-
300
350
µs
CL = 1.1 µF(3)
-
500
650
CL = 1.5 µF(3)
-
650
800
IINRUSH
Control of
maximum DC
current drive on
VREFBUF_OUT
during start-up
phase (4)
--
-
8
-
mA
IDDA
(VREFBUF)
VREFBUF
consumption
from VDDA
Iload = 0 µA
-
16
25
µA
Iload = 500 µA
-
18
30
Iload = 4 mA
-
35
50
1. Guaranteed by design or characterization. Not tested in production.
2. In degraded mode, VREFBUF cannot maintain accurately the output voltage that follows (VDDA - drop voltage).
3. The capacitive load must include a 100 nF capacitor in order to cut-off the high-frequency noise.
4. To correctly control the VREFBUF in-rush current during start-up phase and scaling change, the VDDA voltage must be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.
Table 83. VREFBUF characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MSv62522V2
2.025
2.03
2.035
2.04
2.045
2.05
2.055
2.06
-40
-20
0
20
40
60
80
100
120
V
°C
Mean
Min
Max



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