ACE25AA320GFMTH datasheet(9/67 Pages) ACE

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ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

Status Register

S15

S14

S13

S12

S11

S10

SUS

CMP

Reserved

SRP1

SRP0

BP4

BP3

BP2

BP1

BP0

WEL

WIP

The status and control bits of the Status Register are as follows:

WIP bit.

The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status

progress, When WIP bit sets 0, means the device is not in program/ erase/ write status register progress.

WEL bit.

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1

the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write

Status Register, Program or Erase command is accepted.

BP4, BP3,BP2, BP1,BP0 bits.

The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Program and Erase commands. These bits are written with the Write Status

relevant memory area (as defined in Table1) becomes protected against Page Program (PP), Sector

Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be

written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is

executed if the Block Protect (BP2, BP1, BP0) bits are 0 and CMP=0 or the Block Protect (BP2, BP1, BP0)

bits are 1 and CMP=1.

SRP1,SRP0 bit.

The Status Register Protect (SRP1 and SRP0) bit is a non-volatile Read/Write bit in the status register.

The SRP bit controls the method of write protection: software protection, hardware protection, power

supply lock-down or one time programmable protection.

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