MP8799AE datasheet(9/20 Pages) EXAR

9 / 20 page

MP8799

Rev. 3.00

Analog Input Multiplexer

The MP8799 includes a 8-Channel analog input multiplexer.

The relationship between the clock, the multiplexer address, the

WR and the output data is shown in

Figure 10.

Figure 10. MUX Address Timing

Clock

DB0-DB9

tCLKS2

tWR

tCLKH2

Address

tAS

tAH

Sample N

Old Address

Sample M

New Address

Sample

M+1

N-2 Valid

N-1 Valid

Old Address

N Valid

Old Address

M Valid

New Address

tCLKS2 = tCLKH2 = 0

A2, A1, A0

MUXEN

(Internal Signal)

tAS

tAH

tWR

tMUXEN1

Figure 11. Analog MUX Timing

Reference Voltages

The input/output relationship is a function of VREF:

AIN = VIN – VREF(–)

VREF = VREF(+) – VREF(–)

DATA = 1023

∗ (A

IN/VREF)

A system can increase total gain by reducing VREF.

Digital Interfaces

The logic encodes the outputs of the comparators into a bi-

nary code and latches the data in a D-type flip-flop for output.

The functional equivalent of the MP8799 (

Figure 12.) is com-

posed of:

Delay stage (tAP) from the clock to the sampling phase

(

S).

An ideal analog switch which samples VIN.

An ideal A/D which tracks and converts VIN with no

delay.

A series of two DFF’s with specified hold (tHLD) and

delay (tDL) times.

tAP, tHLD and tDL are specified in the Electrical Characteristics

table.

Figure 12. MP8799 Functional Equivalent

Circuit and Interface Timing

VIN

A/D

MP8799

CLK

DB9-DB0

N+1

N-1

tDL

tHLD

DB9-DB0

CLK

VIN

tAP

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