LT8331 datasheet(19/24 Pages) AD

19 / 24 page

LT8337/LT8337-1

Rev. 0

For more information www.analog.com

the low parasitic inductance. Additional bulk capacitors

of 2.2µF or more should be placed close to the IC with

the positive terminals connected to VOUT, and negative

terminals connected to ground plane. The bypass capaci-

tors for VIN and INTVCC pins should also be connected to

the ground plane.

The output capacitors, along with the inductor and input

capacitors, should be placed on the same side of the

circuit board, and their connections should be made on

that layer. Place a local, unbroken power ground plane

under the application circuit on the layer closest to the

surface layer. The SW and BST nodes should be as small

as possible.

Keep the FB and RT nodes small so that the ground traces

will shield them from the noise generated by the SW and

BST nodes. It is recommended to use the GND at Pin 3

for the ground connection of the resistors connecting FB

pin or RT Pin (refer to Figure 6).

CVCC

COUT3

VIN

83371 F04

COUT2

COUT1

CBST

CIN1

GROUND VIA

PG SIGNAL VIA

VOUT

GND

Figure 5. Transient Response

Figure 6. A Recommended PCB Layout for the LT8337

VIN = 7.2V

FRONT PAGE CIRCUIT

200µs/DIV

IOUT

1A/DIV

83371 F05a

(a)

VOUT

0.2V/DIV

(AC)

VIN = 7.2V

FRONT PAGE CIRCUIT WITH LT8337-1

CC = 220pF, RC = 100k

200µs/DIV

VOUT

0.2V/DIV

(AC)

IOUT

1A/DIV

83317 F05b

(b)

Board Layout

The LT8337/LT8337-1 is specifically designed to mini-

mize EMI/EMC emissions and also to maximize efficiency

when switching at high frequencies. Figure 6 shows a

recommended PCB layout for LT8337. For more detail

and PCB design files refer to the demo board guide for

the LT8337/LT8337-1.

For optimal performance the LT8337/LT8337-1 requires

the use of multiple VOUT bypass capacitors. It is recom-

mended to connect one 1µF capacitor between VOUT at

Pin 6 and GND at Pin 5 only, and a matching 1µF capacitor

between VOUT at Pin 7 and GND at Pin 8 only to complete

the Silent Switcher EMI cancellation loops. These two

capacitors must be placed as close as possible to the

IC, and the loops formed by these two capacitors should

be symmetrical and as small as possible to achieve an

optimized EMI cancellation performance. Capacitors with

small case size, such as 0402 or 0603, are optimal due to

APPLICATIONS INFORMATION

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