STW4810 datasheet(12/72 Pages) STMICROELECTRONICS

12 / 72 page

4 Functional description

STw4810

12/72

Rev3

EXT_CLK: When MASTER_CLK is detected, the STw4810 uses this clock as reference and

switches off its internal oscillator to save quiescent. MASTERCLK should remain connected up

to SLEEP mode.

SLEEP: SLEEP mode is required by multimedia processor by setting a PWREN at low level.

Then VDDOK is forced to 0, regulators (VCORE, VIO_VMEM) switch to sleep mode and wait

for PWREN at high level (

Figure 4).

WAKE-UP: From SLEEP mode, the multimedia processor requests to switch back to Normal

mode. Thus the device restarts its internal oscillator and then switches regulators from sleep to

normal mode and informs multimedia processor with VDDOK at high level (

Figure 4).

Note:

By default VAUX is in stand by mode, pdn_vaux = 0 (Table 17). It can be programmed in normal

mode only by asserted pdn_vaux bit to “1”.

Figure 3.

Start-up timing

PON ball

PDN__OSC

PDN_regulators

VDDOK ball

CLK32K_IN ball

PORn ball

PWREN ball

OFF

START_PM

RESET

1mS

INT_OSC

TCXO_EN ball

Internal_OSC

10*(1/32KHz)

OFF2

MASTER_CLK ball

REQUEST_MC ball

VBAT

300µs

9.38mS (11mS wc)

RESET

START_BIAS

7.77ms (9.46ms wc)

“or”

Delays are worst case maximum delays

Voutput(s) ball

VPLL / VIO_VMEM

VCORE

CLK32K ball

(*)

(*) If 32 Khz available before VDDOK signal rising edge, OFF2 state duration is null

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