19/25

STM6717/6718/6719/6720/6777/6778/6779*/6780*

2. Input leakage for the MRC pin is not tested.

3. Guaranteed by design.

4. The leakage current measured on the RST pin is tested with the reset de-asserted (output high impedance).

5. Selecting the appropriate external capacitor (preferably less than 100pF) allows systems designers to vary the minimum delay from

6µs (MRC pin left open) or more (see Table 7.).

Note: 1. At 25°C (typical)

Manual (Push-button) Reset Input

MR Input Voltage

V

V

MR Minimum Pulse Width

(STM6717/18/19/20)

1µs

MR Minimum Pulse Width

(STM6777/78/79/80)

MRC connected via

(5)

6µs

MR to RST Output Delay

200

ns

MR Glitch Immunity

(STM6717/18/19/20)

100

ns

MR Pull-up Resistance

25

50

80

k

Ω

100pF

0.1µF

2.2µF

3.3µF

4.7µF

6.8µF

1.6V

120µs

120ms

2.6s

4.0s

5.6s

8.2s

2.0V

122µs

122ms

2.7s

4.0s

5.8s

8.3s

3.0V

125µs

125ms

2.7s

4.1s

5.9s

8.5s

4.0V

128µs

129ms

2.8s

4.2s

6.0s

8.7s

5.0V

130µs

130ms

2.8s

4.3s

6.1s

8.8s

Sym

Alter-

native

Description

Min

Typ

Max

Unit