24CS512TESLASHMS datasheet(25/66 Pages) MICROCHIP

25 / 66 page

 2018-2021 Microchip Technology Inc.

DS20005769C-page 25

24CS512

9.2

Configuration Register Format

Following the word address bytes are the contents of

the 16-bit Configuration register. The Configuration

Error Correction State bit (ECS): This bit is used

when the user needs to determine whether the on-chip

Error Correction Code (ECC) logic scheme has been

invoked. For more information related to ECC, refer to

Section 6.3 “Internal Writing Methodology”. The

ECS bit will be set to logic ‘0’ unless the previously exe-

cuted read operation required the use of the ECC logic

scheme. When this occurs, the ECS bit will set to logic

‘1’. The ECS bit will continue to read a logic ‘1’ until

another read operation is issued and the use of the

ECC logic scheme was not required or a Power-on

Reset (POR) event occurred.

Enhanced Software Write Protection Mode bit

(EWPM): This bit is a feature in which the user can

select between Legacy Hardware Write Protection mode

(logic ‘0’) and Enhanced Software Write Protection

mode (logic ‘1’). Legacy Hardware Write Protection

mode allows the entire memory array to be write-pro-

tected via the WP pin.

Enhanced Software Write Protection is a software

write-protect feature where the memory array is divided

into eight separate 64-Kbit (8192-byte) zones. Each

zone is independent and is configured using the

SWP<7:0> bits (Register 9-2). For additional informa-

tion related to the write protection schemes, refer to

Section 6.6 “Write Protection”.

Lock Configuration Register bit (LOCK): This bit

allows the user to lock the Configuration register so that

it is set to read-only and can no longer be modified,

thereby making the current data protection scheme

permanent. Refer to Section 9.5 “Locking the Con-

figuration Register” for additional information on lock-

ing the Configuration register.

CONFIGURATION REGISTER – BYTE 0

R-0

U-0

R/W

ECS

—

—EWPM

LOCK

bit 15

bit 8

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ECS: Error Correction State bit

1 = The previously executed read operation did require the use of the Error Correction Code (ECC)

scheme

0 = The previously executed read operation did not require the use of the Error Correction Code

(ECC) scheme

bit 14-10

Unimplemented: Read as ‘0’

bit 9

EWPM: Enhanced Software Write Protection Mode bit

1 = Enhanced Protection: WP pin is treated as a don’t care and the memory array is protected in

accordance with the SWP bits defined in Register 9-2

0 = Legacy Protection (factory default): Entire memory array and Security register contents are

24CS512TE/MS Datenblatt(PDF) 25 Page - Microchip Technology

24CS512TE/MS Datenblatt(HTML) 25 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datenblatt Download

Link URL