| Datenblatt-Suchmaschine für elektronische Bauteile |
|
PLL601-01SC-R Datenblatt(PDF) 1 Page - PhaseLink Corporation |
|
|
|||||||||||||||||||||||||||||
PLL601-01SC-R Datenblatt(HTML) 1 Page - PhaseLink Corporation |
|
1 / 5 page ![]() PLL601-01 Low Phase Noise PLL Clock Multiplier 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1 FEATURES • Low phase noise XO • Input from crystal or clock at 10-27MHz. • Integrated crystal load capacitor: no external load capacitor required. • Output clocks up to 160MHz. • Low phase noise (-125dBc/Hz @ 1kHz). • Output Enable function. • Low jitter (RMS): 7.2ps (period), 11.2ps (accum.) • Advanced low power sub-micron CMOS process. • 3.3V operation. • Available in 16-Pin SOIC or TSSOP. DESCRIPTION The PLL601-01 is a low cost, high performance and low phase noise clock synthesizer. Using Phase- Link’s proprietary analog and digital Phase Locked Loop techniques, this IC can produce up to a 160MHz output. PIN CONFIGURATION Note: ^ denotes internal pull up. BLOCK DIAGRAM 1 2 3 4 5 6 7 8 CLK 9 10 11 12 13 14 15 16 REFEN VDD VDD VDD XOUT S1^ XIN GND GND GND REFOUT OE^ S0^ S3^ S2^ Reference Divider Phase Comparator Charge Pump Loop Filter VCO ROM Based Multipliers VCO Divider XTAL OSC CLK REFOUT OE REFEN S3 S2 S1 S0 XIN XOUT |
Ähnliche Teilenummer - PLL601-01SC-R |
|
Ähnliche Beschreibung - PLL601-01SC-R |
|
|
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |