Quad PLL with VCXO for HDTV

MDS 477-05 H

2

Revision 062404

Integrated Circuit Systems, Inc.

ICS477-05

Pin Assignment

Pin Descriptions

17

16

9

15

GN D

12

13

14

GN D

NC

NC

27M

N C

27M

20

74.175M

18

11

GN D

54.054M

GN D

54M

19

10

28 p in (1 50 m il) S S O P

82 1

7

GN D

GN D

G N D

22

V D D

5

VD D

VD D

V D D

24

V D D

23

6

42 5

3

GN D

VIN

G N D

26

P D T S

1

X1

GN D

V D D

28

X 2

27

2

Pin

Number

Pin

Name

Pin Type

Pin Description

1

XI

Input

Crystal connection. Connect to a 27 MHz fundamental mode pullable crystal.

2

GND

Power

Connect to ground.

3

GND

Power

Connect to ground.

4

VIN

Input

VCXO Voltage input. Zero to 3.3 V analog control voltage for VCXO.

5, 6, 22, 23,

24, 27

VDD

Power

Connect to +3.3 V.

7, 8, 9, 10, 19,

20, 21

GND

Power

Connect to ground.

11

54.054M

Output

54.054 MHz clock output. Weak internal pull-down when tri-state.

12, 13, 17

NC

-

No connect. Do not connect anything to these pins.

14

74.175M

Output

74.175 MHz clock output. Weak internal pull-down when tri-state.

15, 16

27M

Output

27 MHz reference clock output. Weak internal pull-down when tri-state.

18

54M

Output

54 MHz clock output. Weak internal pull-down when tri-state.

25

GND

Power

Connect to ground.

26

PDTS

Input

Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up.

28

X2

Input

Crystal connection. Connect to a 27 MHz fundamental mode pullable crystal.