USB7206CTSLASHKDX datasheet(32/56 Pages) MICROCHIP

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DS00003850A-page 32

USB7206C

7.3.1.2

Adaptive OUT 48KHz Streaming

In this mode, the codec sampling clock is initially set to 48Khz based on the local oscillator. The host data is fed into the

OUT FIFO. The host will send the same amount of data on every frame, i.e. 48KHz of data based on the host clock. The

codec sampling clock is asynchronous to the host clock. This will cause the amount of data in the OUT FIFO to vary. If

the amount of data in the FIFO exceeds the high water mark, then the sampling clock is increased. If the data is between

the high and low water mark, the sampling clock does not change. If the data is below the low water mark, the sampling

clock is decreased.

7.3.1.3

Synchronous Operation

For synchronous operation, the internal clock must be synchronized with the host SOF. The Frame SOF is nominally

1mS. Since there is significant jitter in the SOFs, there is circuitry provided to measure the SOFs over a long period of

time to get a more accurate reading. The calculated host frequency is used to calculate the codec sampling clock.

USB7206CT/KDX Datenblatt(PDF) 32 Page - Microchip Technology