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PCIMX6QP6AVT2AB Datenblatt(PDF) 59 Page - NXP Semiconductors |
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PCIMX6QP6AVT2AB Datenblatt(HTML) 59 Page - NXP Semiconductors |
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59 / 166 page ![]() Electrical Characteristics i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018 NXP Semiconductors 59 4.9.3.4 General EIM Timing-Asynchronous Mode Figure 18 through Figure 22 and Table 42 provide timing parameters relative to the chip select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing parameters mentioned above. Asynchronous read and write access length in cycles may vary from what is shown in Figure 18 through Figure 21 as RWSC, OEN & CSN is configured differently. See the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM) for the EIM programming model. Figure 18. Asynchronous Memory Read Access (RWSC = 5) Last Valid Address Address V1 D(V1) EIM_ADDRxx/ EIM_DATA[07:00] EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B EIM_CSx_B Next Address WE39 WE35 WE37 WE32 WE36 WE38 WE43 WE40 WE31 WE44 INT_CLK start of access end of access MAXDI MAXCSO MAXCO EIM_ADxx |
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