PCIMX6DP6AVT2AB datasheet(52/166 Pages) NXP

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i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

4.8.2

DDR I/O Output Buffer Impedance

For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported

DDR3/DDR3L/LPDDR2 Configurations.”

Table 36 shows DDR I/O output buffer impedance of i.MX 6DualPlus/6QuadPlus processors.

Note:

1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.

2. Calibration is done against 240 W external reference resistor.

3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

4.8.3

LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

4.8.4

MLB 6-Pin I/O Differential Output Impedance

Table 37 shows MLB 6-pin I/O differential output impedance of i.MX 6DualPlus/6QuadPlus processors.

Table 36. DDR I/O Output Buffer Impedance

Parameter

Symbol

Test Conditions

Typical

Unit

NVCC_DRAM=1.5 V

(DDR3)

DDR_SEL=11

NVCC_DRAM=1.2 V

(LPDDR2)

DDR_SEL=10

Output Driver

Impedance

Rdrv

Drive Strength (DSE) =

000

001

010

011

100

101

110

111

Hi-Z

240

120

Hi-Z

240

120

Table 37. MLB 6-Pin I/O Differential Output Impedance

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Differential Output Impedance

—1.6

—

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