PCIMX6DP6AVT2AB datasheet(114/166 Pages) NXP

114 / 166 page

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018

114

NXP Semiconductors

Electrical Characteristics

4.12.13.3 Receiver Real-Time Data Flow

Figure 75. Receiver Real-Time Data Flow READY Signal Timing

4.12.13.4 Synchronized Data Flow Transmission with Wake

Figure 76. Synchronized Data Flow Transmission with WAKE

4.12.13.5 Stream Transmission Mode Frame Transfer

Figure 77. Stream Transmission Mode Frame Transfer (Synchronized Data Flow)

N-bits Frame

First bit of

frame

NomBit

Last bit of

frame

First bit of

frame

Last bit of

frame

DATA

FLAG

READY

Receiver has

detected the start

of the Frame

Receiver has captured a

complete Frame

DATA

FLAG

READY

1. Transmitter has

data to transmit

3. First bit

received

PHY Frame

TX state

RX state

WAKE

2. Receiver in active

start state

4. Received

frame stored

5. Transmitter

has no more

data to

transmit

6. Receiver

can no longer

receive date

A: Sleep state(non-operational)

B: Wake-up state

C: Active state (full operational)

D: Disable State(No communication ability)

Complete N-bits Frame

DATA

FLAG

READY

Channel

Description

bits

Payload Data Bits

PCIMX6DP6AVT2AB Datenblatt(PDF) 114 Page - NXP Semiconductors

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