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PCIMX6DP4AVT2AB Datenblatt(PDF) 139 Page - NXP Semiconductors

Teilenummer PCIMX6DP4AVT2AB
Bauteilbeschribung  i.MX 6DualPlus/6QuadPlus Automotive Applications Processors
PDF  166 Pages
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Hersteller  NXP [NXP Semiconductors]
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Boot Mode Configuration
i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
NXP Semiconductors
139
5.2
Boot Devices Interfaces Allocation
Table 94 lists the interfaces that can be used by the boot process in accordance with the specific boot
mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
EIM_A19
Input
BOOT_CFG3[3]
EIM_A20
Input
BOOT_CFG3[4]
EIM_A21
Input
BOOT_CFG3[5]
EIM_A22
Input
BOOT_CFG3[6]
EIM_A23
Input
BOOT_CFG3[7]
EIM_A24
Input
BOOT_CFG4[0]
EIM_WAIT
Input
BOOT_CFG4[1]
EIM_LBA
Input
BOOT_CFG4[2]
EIM_EB0
Input
BOOT_CFG4[3]
EIM_EB1
Input
BOOT_CFG4[4]
EIM_RW
Input
BOOT_CFG4[5]
EIM_EB2
Input
BOOT_CFG4[6]
EIM_EB3
Input
BOOT_CFG4[7]
1 Pin value overrides fuse settings for BT_FUSE_SEL = ‘0’. Signal Configuration as Fuse Override Input at Power
Up. These are special I/O lines that control the boot up configuration during product development. In production,
the boot configuration can be controlled by fuses.
Table 94. Interfaces Allocation During Boot
Interface
IP Instance
Allocated Pads During Boot
Comment
SPI
ECSPI-1
EIM_D17, EIM_D18, EIM_D16, EIM_EB2, EIM_D19,
EIM_D24, EIM_D25
—
SPI
ECSPI-2
CSI0_DAT10, CSI0_DAT9, CSI0_DAT8, CSI0_DAT11,
EIM_LBA, EIM_D24, EIM_D25
—
SPI
ECSPI-3
DISP0_DAT2, DISP0_DAT1, DISP0_DAT0,
DISP0_DAT3,DISP0_DAT4,DISP0_DAT5,DISP0_DAT6
—
SPI
ECSPI-4
EIM_D22, EIM_D28, EIM_D21, EIM_D20, EIM_A25,
EIM_D24, EIM_D25
—
SPI
ECSPI-5
SD1_DAT0, SD1_CMD, SD1_CLK, SD1_DAT1,
SD1_DAT2, SD1_DAT3, SD2_DAT3
—
EIM
EIM
EIM_DA[15:0], EIM_D[31:16], CSI0_DAT[19:4],
CSI0_DATA_EN, CSI0_VSYNC
Used for NOR, OneNAND boot
Only CS0 is supported
Table 93. Fuses and Associated Pins Used for Boot (continued)
Pin
Direction at Reset
eFuse Name



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