PCIMX6DP4AVT2AB datasheet(56/168 Pages) NXP

56 / 168 page

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

WE4

Clock rise to address valid

-0.5

× t × (k+1) - 1.25

-0.5

× t × (k+1) + 2.25

WE5

Clock rise to address invalid

0.5

× t × (k+1) - 1.25

0.5

× t × (k+1) + 2.25

WE6

Clock rise to EIM_CSx_B valid

-0.5

× t × (k+1) - 1.25

-0.5

× t × (k+1) + 2.25

WE7

Clock rise to EIM_CSx_B invalid

0.5

× t × (k+1) - 1.25

0.5

× t × (k+1) + 2.25

WE8

Clock rise to EIM_WE_B valid

-0.5

× t × (k+1) - 1.25

-0.5

× t × (k+1) + 2.25

WE9

Clock rise to EIM_WE_B invalid

0.5

× t × (k+1) - 1.25

0.5

× t × (k+1) + 2.25

WE10

Clock rise to EIM_OE_B valid

-0.5

× t × (k+1) - 1.25

-0.5

× t × (k+1) + 2.25

WE11

Clock rise to EIM_OE_B invalid

0.5

× t × (k+1) - 1.25

0.5

× t × (k+1) + 2.25

WE12

Clock rise to EIM_EBx_B valid

-0.5

× t × (k+1) - 1.25

-0.5

× t × (k+1) + 2.25

WE13

Clock rise to EIM_EBx_B invalid

0.5

× t × (k+1) - 1.25

0.5

× t × (k+1) + 2.25

WE14

Clock rise to EIM_LBA_B valid

-0.5

× t × (k+1) - 1.25

-0.5

× t × (k+1) + 2.25

WE15

Clock rise to EIM_LBA_B invalid

0.5

× t × (k+1) - 1.25

0.5

× t × (k+1) + 2.25

WE16

Clock rise to output data valid

-0.5

× t × (k+1) - 1.25

-0.5

× t × (k+1) + 2.25

WE17

Clock rise to output data invalid

0.5

× t × (k+1) - 1.25

0.5

× t × (k+1) + 2.25

WE18

Input data setup time to clock rise

2.3

—

WE19

Input data hold time from clock rise

—

WE20

EIM_WAIT_B setup time to clock rise

—

WE21

EIM_WAIT_B hold time from clock rise

—

1 k represents register setting BCD value.

2 t is clock period (1/Freq). For 104 MHz, t = 9.165 ns.

Table 41. EIM Bus Timing Parameters (continued)

Parameter

Min1

Max1

Unit

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