PCIMX6DP4AVT2AB datasheet(119/168 Pages) NXP

119 / 168 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

119

Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing

parameters specified from the valid voltage threshold as listed in Table 74; unless otherwise noted.

Table 75 lists the MediaLB 6-pin interface timing characteristics, and Figure 82 shows the MLB 6-pin

delay, setup, and hold times.

Bus Hold from MLB_CLK low

tmdzh

4—

—

Transmitter MLBSIG (MLBDAT)

output valid from transition of

MLBCLK (low-to-high)

Tdelay

—

10.75

—

1 The controller can shut off MLB_CLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a

runt pulse can occur on MLB_CLK.

2 MLB_CLK low/high time includes the pulse width variation.

3 The MediaLB driver can release the MLB_DATA/MLB_SIG line as soon as MLB_CLK is low; however, the logic state of the

final driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the maximum

load capacitance listed.

Table 74. MLB 1024 Fs Timing Parameters

Parameter

Symbol

Min

Max

Unit

Comment

MLB_CLK Operating Frequency1

1 The controller can shut off MLB_CLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a

runt pulse can occur on MLB_CLK.

fmck

45.056

51.2

MHz

1024xfs at 44.0 kHz

1024xfs at 50.0 kHz

MLB_CLK rise time

tmckr

—1

VIL TO VIH

MLB_CLK fall time

tmckf

—1

VIH TO VIL

MLB_CLK low time

tmckl

6.1

—

(see 2)

2 MLB_CLK low/high time includes the pulse width variation.

MLB_CLK high time

tmckh

9.3

—

MLB_SIG/MLB_DATA receiver input valid to

MLB_CLK falling

tdsmcf

1—

—

MLB_SIG/MLB_DATA receiver input hold

from MLB_CLK low

tdhmcf

tmdzh

—ns

—

MLB_SIG/MLB_DATA output high

impedance from MLB_CLK low

tmcfdz

0tmckl

(see 3)

3 The MediaLB driver can release the MLB_DATA/MLB_SIG line as soon as MLB_CLK is low; however, the logic state of the

final driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the maximum

load capacitance listed.

Bus Hold from MLB_CLK low

tmdzh

2—

—

Transmitter MLBSIG (MLBDAT) output valid

from transition of MLBCLK (low-to-high)

Tdelay

—

Table 73. MLB 256/512 Fs Timing Parameters (continued)

Parameter

Symbol

Min

Max

Unit

Comment

PCIMX6DP4AVT2AB Datenblatt(PDF) 119 Page - NXP Semiconductors

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