SCIMX6DP4AVT2AB datasheet(120/168 Pages) NXP

120 / 168 page

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

120

NXP Semiconductors

Electrical Characteristics

Figure 82. MLB 6-Pin Delay, Setup, and Hold Times

4.12.15 PCIe PHY Parameters

The PCIe interface complies with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0

standard.

Table 75. MLB 6-Pin Interface Timing Parameters

Parameter

Symbol

Min

Max

Unit

Comment

Cycle-to-cycle system jitter

tjitter

—

600

—

Transmitter MLB_SIG_P/_N

(MLB_DATA_P/_N) output valid from transition

of MLB_CLK_P/_N (low-to-high)1

1 t

delay, tphz, tplz, tsu, and thd may also be referenced from a low-to-high transition of the recovered clock for 2:1 and 4:1 recov-

ered-to-external clock ratios.

tdelay

0.6

1.3

—

Disable turnaround time from transition of

MLB_CLK_P/_N (low-to-high)

tphz

0.6

3.5

—

Enable turnaround time from transition of

MLB_CLK_P/_N (low-to-high)

tplz

0.6

5.6

—

MLB_SIG_P/_N (MLB_DATA_P/_N) valid to

transition of MLB_CLK_P/_N (low-to-high)

tsu

0.05

—

MLB_SIG_P/_N (MLB_DATA_P/_N) hold from

transition of MLB_CLK_P/_N (low-to-high)2

2 The transmitting device must ensure valid data on MLB_SIG_P/_N (MLB_DATA_P/_N) for at least t

hd(min) following the rising

edge of MLBCP/N; receivers must latch MLB_SIG_P/_N (MLB_DATA_P/_N) data within thd(min) of the rising edge of MLB_-

CLK_P/_N.

thd

0.6

—

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