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SCIMX6DP5AVT2AB Datenblatt(PDF) 42 Page - NXP Semiconductors |
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SCIMX6DP5AVT2AB Datenblatt(HTML) 42 Page - NXP Semiconductors |
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42 / 160 page ![]() i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 42 NXP Semiconductors Electrical Characteristics 4.6.5 LVDS I/O DC Parameters The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details. Table 25 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters. 4.7 I/O AC Parameters This section includes the AC parameters of the following I/O types: • General Purpose I/O (GPIO) • Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes •LVDS I/O The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. DC input Logic High Vih(dc) — Vref+0.1 OVDD V DC input Logic Low Vil(dc) — OVSS Vref-0.1 V Differential input Logic High Vih(diff) — 0.2 See Note3 V Differential input Logic Low Vil(diff) — See Note3 -0.2 V Termination Voltage Vtt Vtt tracking OVDD/2 0.49 × OVDD 0.51 × OVDD V Input current (no pull-up/down) Iin Vin = 0 or OVDD -2.9 2.9 μA Pull-up/pull-down impedance mismatch MMpupd —-10 10 % 240 Ω unit calibration resolution Rres — — 10 Ω Keeper circuit resistance Rkeep — 105 175 k Ω 1 OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L). 2 Vref – DDR3/DDR3L external reference voltage. 3 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot (see Table 29). Table 25. LVDS I/O DC Parameters Parameter Symbol Test Conditions Min Max Unit Output Differential Voltage VOD Rload=100 Ω between padP and padN 250 450 mV Output High Voltage VOH IOH = 0 mA 1.25 1.6 V Output Low Voltage VOL IOL = 0 mA 0.9 1.25 Offset Voltage VOS — 1.125 1.375 Table 24. DDR3/DDR3L I/O DC Electrical Parameters (continued) Parameters Symbol Test Conditions Min Max Unit |
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