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SCIMX6DP5AVT2AB Datenblatt(PDF) 110 Page - NXP Semiconductors |
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SCIMX6DP5AVT2AB Datenblatt(HTML) 110 Page - NXP Semiconductors |
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110 / 160 page ![]() i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 110 NXP Semiconductors Electrical Characteristics 4.12.12.6 High-Speed Clock Timing Figure 67. DDR Clock Definition 4.12.12.7 Forward High-Speed Data Transmission Timing The timing relationship of the DDR Clock differential signal to the Data differential signal is shown in Figure 68: Figure 68. Data to Clock Timing Definitions 4.12.12.8 Reverse High-Speed Data Transmission Timing Figure 69. Reverse High-Speed Data Transmission Timing at Slave Side LS Equivalent wire bond series inductance — — — 1.5 nH RS Equivalent wire bond series resistance — — — 0.15 Ω RL Load Resistance — 80 100 125 Ω Table 65. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit 1 Data Bit Time = 1UI UIINST(1) 1 Data Bit Time = 1UI UIINST(2) CLKp CLKn 1 DDR Clock Period = UIINST(1) + UIINST(2) TTD 2UI 2UI CLKp CLKn Clock to Data Skew NRZ Data |
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