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SCIMX6QP4AVT2AB Datenblatt(PDF) 70 Page - NXP Semiconductors |
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SCIMX6QP4AVT2AB Datenblatt(HTML) 70 Page - NXP Semiconductors |
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70 / 160 page ![]() i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 70 NXP Semiconductors Electrical Characteristics Figure 32. Samsung Toggle Mode Data Read Timing Table 42. Samsung Toggle Mode Timing Parameters1 ID Parameter Symbol Timing T = GPMI Clock Cycle Unit Min Max NF1 NAND_CLE setup time tCLS (AS + DS) × T - 0.12 [see 2,3]— NF2 NAND_CLE hold time tCLH DH × T - 0.72 [see 2]— NF3 NAND_CEx_B setup time tCS (AS + DS) × T - 0.58 [see 3,2]— NF4 NAND_CEx_B hold time tCH DH × T - 1 [see 2]— NF5 NAND_WE_B pulse width tWP DS × T [see 2]— NF6 NAND_ALE setup time tALS (AS + DS) × T - 0.49 [see 3,2]— NF7 NAND_ALE hold time tALH DH × T - 0.42 [see 2]— NF8 Command/address NAND_DATAxx setup time tCAS DS × T - 0.26 [see 2]— NF9 Command/address NAND_DATAxx hold time tCAH DH × T - 1.37 [see 2]— NF18 NAND_CEx_B access time tCE CE_DELAY × T [see 4,2]— ns NF22 clock period tCK — — ns NF23 preamble delay tPRE PRE_DELAY × T [see 5,2]— ns NF24 postamble delay tPOST POST_DELAY × T +0.43 [see 2]— ns |
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