PD70100 datasheet(19/30 Pages) MICROCHIP

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Pin Number

Pin Name

Description

RREF

Bias current resistor. A 60.4 KΩ 1% resistor is connected between RREF

and IC ground (VPN_IN).

RCLS

Sets the class of the PD. Connect RCLASS (programming resistor) between

this pin and IC ground (VPN_IN). Allowed values are 133 Ω, 69.8 Ω, 45.3

Ω, and 30.9 Ω for Class 1, 2, 3, and 4, respectively. If RCLASS is not

present, the PD will draw up to 3 mA during classification, indicating Class 0

(default type 1) to the PSE. Signal is referenced to VPN_IN.

9, 10

11, 12

VPN_IN

Lower rail of the incoming PSE voltage rail, from the negative terminal of

the two OR-ed bridge rectifiers. The corresponding upper PoE rail is VPP.

13, 14

No connect.

16, 17

VPN_OUT

In effect, the switched ground for establishing continuity to the PWM section

after successful detection, classification, and power-up. It is connected to

the power ground and PWM controller IC’s ground plane of the DC–DC

converter section.

18, 19

20, 21, 22, 23

No connect.

AT_FLAG

Open drain output. This pin gets actively pulled low when a type 2 PD-PSE

mutually identifies each other through classification. There is a minimum 80

ms delay from the moment that the input capacitor is fully charged to this

signal activity. Signal is referenced to VPN_OUT.

HD_FLAG

Open drain output. This pin gets actively pulled low when a 2-pair HDBaseT

PD-PSE mutually identifies each other through classification. There is a

minimum 80 ms delay from the moment that the input capacitor is fully

charged to this signal activity. Signal is referenced to VPN_OUT.

4P_AT_FLAG

Open drain output. This pin gets actively pulled low when a 4-pair version of

a (non-standard) type 2 PD-PSE mutually identifies each other through

classification. There is a minimum 80 ms delay from the moment that the

input capacitor is fully charged to this signal activity. Signal is referenced to

VPN_OUT.

4P_HD_FLAG

Open drain output. This pin gets actively pulled low when a 4-pair HDBaseT

PD-PSE mutually identifies each other through classification. There is a

minimum 80 ms delay from the moment that the input capacitor is fully

charged to this signal activity. Signal is referenced to VPN_OUT.

WA_EN

While this input is low (referenced to VPN_IN), the chip works according to

internal flow diagram. When this input is high, it enables the wall adapter

feature. Place from 100 nF/10 V to 1 μF/10 V capacitor from WA_EN to

VPN_IN pins, close to the device. When WA_EN is not used, connect it to

VPN_IN. For more information, see Figure 1-3.

29,30

VAUX

Auxiliary voltage rail. This is used to provide a few mA of startup current for

the PWM controller (typically, 10.5 V). Signal is referenced to VPN_OUT

and is activated once the front-end power-up sequence ends. DC–DC

should not start up until Vaux is active.

32, 33

PD70210/PD70210A/PD70210AL

Pin Descriptions

Datasheet

DS00003695A-page 19

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