MP7641AS datasheet(9/24 Pages) EXAR

9 / 24 page

MP7641

Rev. 2.00

THEORY OF OPERATION

The MP7641 is equipped with a serial data 3-wire standard

µ-processor logic interface to reduce pin count, package size,

and board wire (space). This interface consists of LD which con-

trols the transfer of data to the selected DAC channel, SDI (serial

data/address input), CLK (shift register clock) and SDO (serial

data output). When the LD signal is high, CLK signal loads the

digital input bits (SDI) into the 12-bit shift register (4 bits address

A3 to A0, then 8 bits data D7 to D0). The LD signal going low

loads this data into the selected DAC. The LD signal going low

also disables the serial data input (SDI), output (SDO 3-stated)

and the CLK input. This design tremendously reduces digital

noise, and glitch transients into the DACs due to free running

CLK and SDI. Also, 3-stating the SDO output with LD signal

would allow read back of pre-stored digital data of the selected

package using one SDO wire for all DAC ICs on the board. Note

also that the reset signal (RST) resets all analog outputs to 1/2 of

VREF, regardless of any digital inputs. Note that the input VRi is

referenced to AGND.

Function

A3 A2 A1 A0

CLK

RST

Shift Data In

and Out

→1

Repeat

Load DACs

DAC 0

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

DAC 6

DAC 7

→0

Reset all DACs to

VREF/2

Table 1. Digital Function Truth Table

Serial In/Serial Out

No Operation

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

MSB

LSB

DAC Output Voltage

VOi = AGND + (VRi – AGND) (

)

256

0000

AGND

(

)

256

1111

000

Table 2. DAC Transfer Function

Analog Output vs. Digital Code

→0

SDI

Data Input

Valid

SDO

Data Output

Valid

Hi-Z

No Operation

Stop Shifting

Data In and

Out

Hi-Z

No Operation

(VRi – AGND)

+ AGND

()

256

(VRi – AGND)

+ AGND

()

256

(VRi – AGND)

+ AGND

255

254

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