SC660E
SMBus System Clock Buffer for Mobile Applications
Cypress Semiconductor Corporation
3901 North First Street
Document#: 38-07025 Rev. *A
12/17/2002
San Jose, CA 95134. Tel: 408-043-2600
Page 2 of 8
http://www.cypress.com
Pin Description
PIN
No.
Pin
Name
PWR
I/O
TYPE
Description
9
FIN
-
I
PAD
This pin is connected to the input reference clock. This clock
must be in the range of 10.0 to 100.0 Mhz.
2,3,6,7,1
1,18,22,2
3,26,27
SDRAM(0:9)
VDDB
O
BUF1
Low skew output clocks.
20
OE
-
I
PAD
Buffer Output Enable pin. This pin is low it is used to place
all output clocks (CLK1:10) in a tri state condition. This
feature facilitates in production board level testing to be
easily implemented for the clocks that this device produces.
Has internal pull-up resistor.
14
SDATA
VDD
I/O
PAD
Serial Data for SMBus control interface. This pin receives
data streams from the SMBus bus and outputs an
acknowledge for valid data.
15
SCLOCK
VDD
I
PAD
Serial Clock for SMBus control interface.
4, 8, 12,
16, 17,
21, 25
VSS
PWR
-
Ground pins for clock output buffers. These pins must be
returned to the same potential to reduce output clock skew.
1, 5, 10,
19, 24,
28
VDDB
-
PWR
-
Power for output clock buffers.
13
VDD
-
PWR
-
Pin for device core logic.
Maximum Ratings
1
1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Voltage Relative to VSS:
-0.3V
Voltage Relative to VDD:
0.3V
Storage Temperature:
-65ºC to + 150ºC
Operating Temperature:
-40ºC to +85ºC
Maximum Power Supply:
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
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