MXC62320GP datasheet(8/8 Pages) MEMSIC

8 / 8 page

MEMSIC MXC6232xG/H/M/N Rev.A

Page 8 of 8

4/11/2010

Sixth cycle: Master device calls Memsic device address

with a READ (8th SCL cycle SDA line high). Memsic

device should acknowledge at the end.

Seventh cycle: Master device cycles SCL line, first

addressed memory data appears on SDA line. If in step 7,

“[00000000]” was sent, internal control register data should

appear (in the following steps, this case is assumed). Master

device should send acknowledge at the end.

Eighth cycle: Master device continues cycle SCL line, next

byte of internal memory should appear on SDA line (MSB

of X channel). The internal memory address pointer

automatically

moves

the

byte.

Master

acknowledges.

Ninth cycle: LSB of X channel. In the case that TOEN bit

of internal register was set to “1”, the MSB and LSB of

TOUT (temperature) should appear in last two steps.

Tenth cycle: MSB of Y channel.

Eleventh cycle: LSB of Y channel.

Master ends communications by sending NO acknowledge

and followed by a STOP command. Note: if mater device

continues to cycle SCL line, the memory pointer will go to

sixth

and

seventh

positions,

which

always

have

“[00000000]”. After seventh position, pointer will go to

zero again.

Optional: Master powers down Memsic device by writing

into internal control register. (See step 1 through 4 for

WRITE operation)

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