ST1S40 datasheet(18/30 Pages) STMICROELECTRONICS

18 / 30 page

Application information

ST1S40

18/30

DocID17928 Rev 6

Figure 7. Switching losses

6.5

Layout consideration

The PC board layout of switching DC-DC regulator is very important in order to minimize the

noise injected in high impedance nodes, to reduce interferences generated by the high

switching current loops, and to optimize the reliability of the device.

In order to avoid EMC problems, the high switching current loops must be as short as

possible. In the buck converter there are two high switching current loops: during the ON

time, the pulsed current flows through the input capacitor, the high side power switch, the

inductor and the output capacitor; during the OFF time, through the low side power switch,

the inductor and the output capacitor.

The input capacitor connected to VINSW must be placed as close as possible to the device,

to avoid spikes on VINSW due to the stray inductance and the pulsed input current.

In order to prevent dynamic unbalance between VINSW and VINA, the trace connecting the

VINA pin to the input must be derived from VINSW and design local ceramic bypass

capacitor (1 µF) as close as possible to the VINA pin.

The feedback pin (FB) connection to the external resistor divider is a high impedance node,

so the interferences can be minimized through the routing of the feedback node with a very

short trace and as far as possible from the high current paths.

A single point connection from signal ground to power ground is suggested.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal

resistance junction to ambient; so a large ground plane, soldered to the exposed pad,

enhances the thermal performance of the converter allowing high power conversion.

VSW

ISW,HS

VIN

VDS,HS

PCOND,HS

PCOND,LS

PSW

TFALL

TRISE

ST1S40 Datenblatt(PDF) 18 Page - STMicroelectronics