AD630ADZ datasheet(13/20 Pages) AD

13 / 20 page

Data Sheet

AD630

Rev. G | Page 13 of 20

CIRCUIT DESCRIPTION

The simplified schematic of the AD630 is shown in Figure 24. It

has been subdivided into three major sections, the comparator,

the two input stages, and the output integrator. The comparator

consists of a front end made up of Q52 and Q53, a flip-flop load

formed by Q3 and Q4, and two current steering switching cells

Q28, Q29 and Q30, Q31. This structure is designed so that a

differential input voltage greater than 1.5 mV in magnitude

applied to the comparator inputs completely selects one of the

switching cells. The sign of this input voltage determines which

of the two switching cells is selected.

The collectors of each switching cell connect to an input

transconductance stage. The selected cell conveys bias currents

i22 and i23 to the input stage it controls, causing it to become

active. The deselected cell blocks the bias to its input stage,

which, as a consequence, remains off.

The structure of the transconductance stages is such that it

presents a high impedance at its input terminals and draws no

bias current when deselected. The deselected input does not

interfere with the operation of the selected input ensuring

maximum channel separation.

Another feature of the input structure is that it enhances the

slew rate of the circuit. The current output of the active stage

follows a quasihyperbolic sine relationship to the differential

input voltage. This means that the greater the input voltage, the

harder this stage drives the output integrator, and the faster the

output signal moves. This feature helps ensure rapid, symmetric

settling when switching between inverting and noninverting

closed loop configurations.

The output section of the AD630 includes a current mirror load

(Q24 and Q25), an integrator voltage gain stage (Q32), and a

complementary output buffer (Q44 and Q74). The outputs of

both transconductance stages are connected in parallel to the

current mirror. Because the deselected input stage produces no

output current and presents a high impedance at its outputs, there

is no conflict. The current mirror translates the differential

output current from the active input transconductance

amplifier into single-ended form for the output integrator.

The complementary output driver then buffers the integrator

output to produce a low impedance output.

Figure 24. AD630 Simplified Schematic

SEL A

SEL B

DIFF

OFF ADJ

DIFF

OFF ADJ

COMP

Q74

Q44

CH B–

CH B+

CH A+

CH A–

i55

Q28

Q31

Q30

Q32

C122

C121

i73

i23

–VS

VOUT

Q52

Q53

+VS

Q65

Q34

Q33

Q62

Q35

Q36

Q67

Q70

Q25

Q24

Q29

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