ADM705/ADM706/ADM707/ADM708

Data Sheet

Rev. H | Page 8 of 12

CIRCUIT INFORMATION

POWER FAIL RESET OUTPUT

RESET is an active low output that provides a reset signal to

threshold. An internal timer holds RESET low for 200 ms after

power-on reset signal for the microprocessor. It allows time for

both the power supply and the microprocessor to stabilize after

power-up. The RESET output is guaranteed to remain valid (low)

held in a stable shutdown condition as the power supply voltage

ramps up.

In addition to RESET, an active high RESET output is also available

on the ADM707/ADM708. This is the complement of RESET

and is useful for processors requiring an active high reset signal.

MANUAL RESET

The manual reset input (MR) allows other reset sources, such as

a manual reset switch, to generate a processor reset. The input is

effectively debounced by the timeout period (200 ms typically).

The MR input is TTL-/CMOS-compatible, so it can also be driven

by any logic reset output.

RESET

MR

WDO

MR EXTERNALLY

DRIVEN LOW

Figure 13. RESET, MR, and WDO Timing

WATCHDOG TIMER (ADM705/ADM706)

The watchdog timer circuit can monitor the activity of the micro-

processor to check that it is not stalled in an indefinite loop. An

output line on the processor toggles the watchdog input (WDI)

line. If this line is not toggled within the timeout period (1.60 sec),

then the watchdog output (WDO) goes low. The WDO can be

connected to a nonmaskable interrupt (NMI) on the processor;

therefore, if the watchdog timer times out, an interrupt is gen-

erated. The interrupt service routine then rectifies the problem.

If a RESET signal is required when a timeout occurs, the WDO

must connect to the manual reset input (MR).

The watchdog timer is cleared by either a high to low or a low to

high transition on WDI. It is also cleared by RESET going low;

therefore, the watchdog timeout period begins after RESET

goes high.

whether or not the watchdog timer has timed out. Normally, this

generates an interrupt, but it is overridden by RESET going low.

The watchdog monitor can be deactivated by floating the WDI.

The WDO can then be used as a low line output because it goes

WDI

WDO

RESET

RESET EXTERNALLY

TRIGGERED BY MR

Figure 14. Watchdog Timing

POWER FAIL COMPARATOR

The power fail comparator is an independent comparator that

can monitor the input power supply. The comparator inverting

input is internally connected to a 1.25 V reference voltage. The

noninverting input is available at the PFI input. This input can

monitor the input power supply via a resistive divider network.

When the voltage on the PFI input drops below 1.25 V, the

comparator output (PFO) goes low, indicating a power failure. For

early warning of power failure, the comparator monitors the

preregulator input by choosing an appropriate resistive divider

network. The PFO output can interrupt the processor so a

shutdown procedure is implemented before power is lost.

recommended to connect the PFI pin with a Schottky diode to

the RESET pin as shown in Figure 15. This helps clamping the

PFI pin voltage during device power up and operation.

INPUT

POWER

R1

R2

POWER-FAIL

INPUT

1.25V

PFI

PFO

POWER-FAIL

OUTPUT

ADM705/ADM706/

ADM707/ADM708

RESET

OUTPUT

RESET

Figure 15. Power Fail Comparator