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ADE1202 Datenblatt(PDF) 38 Page - Analog Devices

Teilenummer ADE1202
Bauteilbeschribung  Dual Channel, Configurable, Isolated Digital Input
PDF  42 Pages
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ADE1202 Datenblatt(HTML) 38 Page - Analog Devices

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ADE1202
Data Sheet
Rev. 0 | Page 38 of 42
Bits
Bit Name
Description
Reset
Access
11
COOLDOWN1
Channel 1 is in cool down mode.
0x0
RW1C
10
TSD
Thermal Shutdown Detected.
0x0
RW1C
9
COMFLT
Communication Fault.
0x0
RW1C
8
MEMFLT
Memory Fault. When a memory fault is detected, the user can reconfigure the device.
0x0
RW1C
7
WARNC2
Warning C from Channel 2.
0x0
RW1C
6
WARNB2
Warning B from Channel 2.
0x0
RW1C
5
WARNA2
Warning A from Channel 2.
0x0
RW1C
4
DOUT2
DOUT2.
0x0
RW1C
3
WARNC1
Warning C from Channel 1.
0x0
RW1C
2
WARNB1
Warning B from Channel 1.
0x0
RW1C
1
WARNA1
Warning A from Channel 1.
0x0
RW1C
0
DOUT1
DOUT1.
0x0
RW1C
STATUS REGISTER
Address: 0x00D, Reset: 0x4000, Name: STATUS
The bits in this register are not latched and can be polled to determine the current status of the desired event.
Table 31. Bit Descriptions for STATUS
Bits
Bit Name
Description
Reset
Access
15
RESERVED
Reserved.
0x0
R
14
RSTBUSY
RSTBUSY goes from 0 to 1 to indicate that the device has reset and is ready to be programmed
or begin default normal operation. Because this bit is active low, the user can distinguish
between a bad read (0xFFFF) and an initialized device.
0x1
R
13
BUSY
Internal Communications Busy.
0x0
R
12
COOLDOWN2
Channel 2 is in cool down mode.
0x0
R
11
COOLDOWN1
Channel 1 is in cool down mode.
0x0
R
10
TSD
Thermal Shutdown Detected.
0x0
R
9
COMFLT
Communication Fault.
0x0
R
8
MEMFLT
Memory Fault. When a memory fault is detected, the user can reconfigure the device.
0x0
R
7
WARNC2
Warning C from Channel 2.
0x0
R
6
WARNB2
Warning B from Channel 2.
0x0
R
5
WARNA2
Warning A from Channel 2.
0x0
R
4
DOUT2
DOUT2.
0x0
R
3
WARNC1
Warning C from Channel 1.
0x0
R
2
WARNB1
Warning B from Channel 1.
0x0
R
1
WARNA1
Warning A from Channel 1.
0x0
R
0
DOUT1
DOUT1.
0x0
R
ADC REGISTER
Address: 0x00E, Reset: 0x0000, Name: ADC
ADC sample updates at 100 kHz, multiplexed into two channels updated at 50 kHz.
Table 32. Bit Descriptions for ADC
Bits
Bit Name
Description
Reset
Access
[15:8]
ADC2
ADC Channel 2.
0x0
R
[7:0]
ADC1
ADC Channel 1.
0x0
R



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