USB7056 datasheet(36/55 Pages) MICROCHIP

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USB7056

DS00002675F-page 36

 2022 Microchip Technology Inc. and its subsidiaries

Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-

form the following functions:

• Enable SPI Pass-Through Interface

• SPI Write/Read

• Disable SPI Pass-Through Interface

For detailed information on utilizing the USB to SPI bridging feature, refer to the application note “USB to SPI Bridging

with Microchip USB7002 and USB705x Hubs

”, which can be found on the Microchip USB7056 product page at

www.microchip.com/USB7056.

8.10

Link Power Management (LPM)

The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM

states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB

suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.

8.11

Resets

The device includes the following chip-level reset sources:

• Power-On Reset (POR)

• External Chip Reset (RESET_N)

• USB Bus Reset

8.11.1

POWER-ON RESET (POR)

A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the

device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, Power-On

and Configuration Strap Timing.

8.11.2

EXTERNAL CHIP RESET (RESET_N)

A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the

specifications in Section 9.6.3, Reset and Configuration Strap Timing. While reset is asserted, the device (and its asso-

ciated external circuitry) enters Standby Mode and consumes minimal current.

Assertion of RESET_N causes the following:

The PHY is disabled and the differential pairs will be in a high-impedance state.

All transactions immediately terminate; no states are saved.

All internal registers return to the default state.

The external crystal oscillator is halted.

The PLL is halted.

8.11.3

USB BUS RESET

In response to the upstream port signaling a reset to the device, the device performs the following:

Sets default address to 0.

Sets configuration to Unconfigured.

TABLE 8-1:

LPM STATE DEFINITIONS

State

Description

Entry/Exit Time to L0

Suspend

Entry: ~3 ms

Exit: ~2 ms (from start of RESUME)

Sleep

Entry: <10 us

Exit: <50 us

Fully Enabled (On)

Note:

All power supplies must have reached the operating levels mandated in Section 9.2, Operating Condi-

tions**, prior to (or coincident with) the assertion of RESET_N.

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