DP8500 datasheet(51/70 Pages) NSC

Teilenummer	DP8500

Bauteilbeschribung	DP8520A/DP8521A/DP8522A microCMOS Programmable 256k/1M/4M Video RAM Controller/Drivers

PDF	70 Pages

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Hersteller	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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150 AC Timing Parameters DP8520ADP8521ADP8522A (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 VRAMs

per bank including trace capacitance (see Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 and 10 or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 and 10

Difference

8520A21A22A-25

Number

Symbol

Parameter Description

Min

Max

Min

Max

tD1

(AREQ or AREQB Negated to RAS

Negated) Minus (CLK High to RAS

Asserted)

tD2

(CLK High to Refresh RAS Negated)

Minus (CLK High to RAS Asserted)

tD3a

(ADS Asserted to RAS Asserted

(Mode 1)) Minus (AREQ Negated

to RAS Negated)

tD3b

(CLK High to RAS Asserted (Mode 0))

Minus (AREQ Negated to RAS Negated)

tD4

(ECAS Asserted to CAS Asserted)

Minus (ECAS Negated to CAS Negated)

tD5

(CLK to Refresh RAS Asserted) Minus

(CLK to Refresh RAS Negated)

tD6

(AREQ Negated to RAS Negated)

Minus (ADS Asserted to RAS

Asserted ((Mode 1))

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