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34LC02 Datenblatt(PDF) 4 Page - Microchip Technology

Teilenummer 34LC02
Bauteilbeschribung  2-Kbit I2C Serial EEPROM Software Write-Protect
PDF  40 Pages
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Hersteller  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

34LC02 Datenblatt(HTML) 4 Page - Microchip Technology

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34AA02/34LC02
DS20002029G-page 4
 2007-2022 Microchip Technology Inc. and its subsidiaries
TABLE 1-2:
AC SPECIFICATIONS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): TA = -40°C to +85°C
Extended (E): TA = -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1FCLK
Clock Frequency
—
100
kHz
1.7V
 VCC < 1.8V
—
400
kHz
1.8V
 VCC  5.5V
—
1000
kHz
2.5V
 VCC  5.5V (34LC02)
2THIGH
Clock High Time
4000
—
ns
1.7V
 VCC < 1.8V
600
—
ns
1.8V
 VCC  5.5V
500
—
ns
2.5V
 VCC  5.5V (34LC02)
3TLOW
Clock Low Time
4700
—
ns
1.7V
 VCC < 1.8V
1300
—
ns
1.8V
 VCC  5.5V
500
—
ns
2.5V
 VCC  5.5V (34LC02)
4TR
SDA and SCL Rise Time
—
1000
ns
1.7V
 VCC < 1.8V (Note 1)
—
300
ns
1.8V
 VCC  5.5V (Note 1)
—
300
ns
2.5V
 VCC  5.5V (34LC02)
(Note 1)
5TF
SDA and SCL Fall Time
—
1000
ns
1.7V
 VCC < 1.8V (Note 1)
—
300
ns
1.8V
 VCC  5.5V (Note 1)
—
300
ns
2.5V
 VCC  5.5V (34LC02)
(Note 1)
6
Thd:sta
Start Condition Hold Time
4000
—
ns
1.7V
 VCC < 1.8V
600
—
ns
1.8V
 VCC  5.5V
250
—
ns
2.5V
 VCC  5.5V (34LC02)
7TSU:STA
Start Condition Setup Time
4700
—
ns
1.7V
 VCC < 1.8V
600
—
ns
1.8V
 VCC  5.5V
250
—
ns
2.5V
 VCC  5.5V (34LC02)
8THD:DAT
Data Input Hold Time
0
—
ns
Note 2
9TSU:DAT
Data Input Setup Time
250
—
ns
1.7V
 VCC < 1.8V
100
—
ns
1.8V
 VCC  5.5V
100
—
ns
2.5V
 VCC  5.5V (34LC02)
10
TSU:STO
Stop Condition Setup Time
4000
—
ns
1.7V
 VCC < 1.8V
600
—
ns
1.8V
 VCC  5.5V
250
—
ns
2.5V
 VCC  5.5V (34LC02)
11
TSU:WP
WP Setup Time
4000
—
ns
1.7V
 VCC < 1.8V
600
—
ns
1.8V
 VCC  5.5V
600
—
ns
2.5V
 VCC  5.5V (34LC02)
12
THD:WP
WP Hold Time
4700
—
ns
1.7V
 VCC < 1.8V
600
—
ns
1.8V
 VCC  5.5V
600
—
ns
2.5V
 VCC  5.5V (34LC02)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization.



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