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High Speed CMOS Logic – 54HC154

Rev 1.0

30/05/22

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

1.9

1.9

1.9

4.5V

4.4

4.4

4.4

6.0V

5.9

5.9

5.9

4.5V

3.98

3.84

3.70

Minimum High-Level

Output Voltage

6.0V

5.48

5.34

5.20

V

2.0V

0.1

0.1

0.1

4.5V

0.1

0.1

0.1

6.0V

0.1

0.1

0.1

4.5V

0.26

0.33

0.40

Maximum Low-Level

Output Voltage

6.0V

0.26

0.33

0.40

V

Maximum Input

Leakage Current

6.0V

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Current

6.0V

8

80

160

µA

6. Not production tested in die form, characterized by chip design and tested in package.

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

190

240

285

4.5V

38

48

57

Maximum

Propagation Delay,

Select to Output Y

(Figure 1, 3)

6.0V

32

41

48

ns

2.0V

175

220

265

4.5V

35

44

53

Maximum

Propagation Delay,

Input A to Output Y

(Figure 2,3)

6.0V

30

37

45

ns

2.0V

75

95

110

4.5V

15

19

22

Maximum Output

Transition Time,

Any Output

(Figure 1,3)

6.0V

13

16

19

ns

Maximum Input

Capacitance

-

-

10

10

10

pF

TYPICAL

Power Dissipation

Capacitance

7

-

80

pF