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L6711

11 SOFT START

During soft start, a ramp is generated increasing the loop reference from 0V to the final value programmed

by VID in 2048 clock periods as shown in

Figure 16. Once the soft start begins, the reference is increased: upper and lower MOS begin to switch

and the output voltage starts to increase with closed loop regulation. At the end of the digital soft start, the

SS_END signal is then driven high.

The Under Voltage comparator is enabled when the reference voltage reaches 0.6V while Over Voltage

Comparator is always enabled during soft start with a threshold equal to the 115% of the programmed ref-

Figure 16. Soft Start

12 OUTPUT VOLTAGE MONITOR AND PROTECTIONS

The device monitors through pin VSEN the regulated voltage in order to manage the OVP / UVP condi-

tions.

12.1 UVP Protection

If the output voltage monitored by VSEN drops below the 60% of the reference voltage for more than one

clock period, the device turns off all mosfets and the OSC/FAULT is driven high (5V). The condition is

latched; to recover it is required to cycle Vcc or the OUTEN pin.

12.2 Programmable OVP Protection

Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), the device provides a

programmable Over Voltage protection; when the voltage sensed overcomes the programmed threshold,

the controller permanently switches on all the low-side mosfets and switches off all the high-side mosfets

in order to protect the load. The OSC/ FAULT pin is driven high (5V) and power supply or OUTEN pin cy-

cling is required to restart operations.

The OVP threshold is programmed through the OVP pin: leaving the pin floating, it is internally pulled-up

and the threshold is set at 115% (Typ.) of the programmed output voltage. Connecting the OVP pin to

µ

12.3 Preliminary OVP Protection (Pre-OVP)

While VCC pin is under the turn-ON threshold, a preliminary-OVP protection turns on the low side mosfets

as long as the FBR pin voltage is greater than 1.8V. This protection is enabled when VCC stays within the

SS_END

t

t

t

t

Turn ON threshold

2048 Clock Cycles

(CH1=VOUT; CH2=LGATEx; CH3=SS_END)