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ZMOD4450AI2 Datenblatt(PDF) 13 Page - Renesas Technology Corp |
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ZMOD4450AI2 Datenblatt(HTML) 13 Page - Renesas Technology Corp |
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13 / 22 page ![]() ZMOD4450 Datasheet © 2021 Renesas Electronics Corporation 13 June 30, 2021 10. I2C Interface and Data Transmission Protocol The I2C slave device interface supports various bus speeds: Standard Mode (≤100kHz) and Fast Mode (≤400kHz). By default, the 7-bit slave address for the serial I2C data interface is set to 32 HEX. The implemented data transmission protocol is similar to the one used for conventional EEPROM devices. The register to read/write is selected by a register address pointer. This address pointer must be set during an I2C write operation. For read access a repeated START condition but no STOP condition should be sent. After transmission of a register, the address pointer is automatically incremented. An increment from the address FFHEX rolls over to 00 HEX. For an example of the I2C data transmission protocol, see Figure 5. For information on I2C bus timing, see Figure 6. For I2C bus characteristics, see Table 9, which explains how to set up the interface. All other values are according to the I2C standard. Although the ZMOD4410 has an I2C interface, the user is not intended to modify any registers because a configuration change will affect the sensor module’s performance, reliability, and accuracy. The API provided with the downloadable firmware package on the website manages all necessary sensor module communication. To validate the general MCU-specific I2C read/write driver without the use of Renesas libraries, it is possible to write random values to registers 0x88 to 0x8B and read them afterwards. After this register testing, erase the testing code and reset the device by disconnecting the power support; otherwise the device may not operate properly. Figure 5. I2C Data Transmission Protocol Write Read Write From master to slave From slave to master S START condition P STOP condition A N Acknowledge Not acknowledge WRITE Access RAM READ Access NVM and RAM 0 S Slave Addr 7 Bit 1 A Address 8 Bit N P Data 8 Bit A S Slave Addr 7 Bit A A Data 8 Bit A Data 8 Bit ... 0 S Slave Addr 7 Bit A Address P Data 8 Bit A A Data 8 Bit A Data 8 Bit ... A |
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