A6278 datasheet(4/18 Pages) ALLEGRO

4 / 18 page

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278 and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

OPERATING CHARACTERISTICS

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max

Unit

ELECTRICAL CHARACTERISTICS valid at TA = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted

LOGIC SUPPLY Voltage Range

VDD

Operating

3.0

5.0

5.5

Undervoltage Lockout

VDD(UV)

VDD = 0.0 → 5.0 V

2.4

–

2.85

VDD = 5.0 → 0.0 V

2.15

–

2.55

Output Current (any single output)

VCE = 0.7 V, REXT = 225 Ω

64.2

75.5

86.8

VCE = 0.7 V, REXT = 470 Ω

34.1

40.0

45.9

VCE = 0.6 V, REXT = 3900 Ω

4.25

5.0

5.75

Output Current Matching (difference between any two

outputs at the same VCE )

ΔIO

VCE(A) = VCE(B) = 0.7 V, REXT = 225 Ω

–+1.0

+6.0

VCE(A) = VCE(B) = 0.7 V, REXT = 470 Ω

–+1.0

+6.0

VCE(A) = VCE(B) = 0.6 V, REXT = 3900 Ω

–+1.0

+6.0

Output Leakage Current

ICEX

VOH = 15 V

–

1.0

5.0

μA

Logic Input Voltage

VIH

0.7VDD

–VDD

VIL

GND

–

0.3VDD

Logic Input Voltage Hysteresis

VIhys

All digital inputs

200

–

400

SERIAL DATA OUT Voltage

VOL

IOL = 500 μA

–

0.4

VOH

IOH = –500 μAVDD–0.4

–

Input Resistance

OUTPUT ENABLE input, Pull Up

150

300

600

kΩ

LATCH ENABLE input, Pull Down

100

200

400

kΩ

LOGIC SUPPLY Current

IDD(OFF)

REXT = open, VOE = 5 V

–

1.4

REXT = 470 Ω, VOE = 5 V

–

5.0

REXT = 225 Ω, VOE = 5 V

–

8.0

IDD(ON)

REXT = 3900 Ω, VOE = 0 V

–

3.0

REXT = 470 Ω, VOE = 0 V

–

18.0

REXT = 225 Ω, VOE = 0 V

–

32.0

Thermal Shutdown Temperature

TJTSD

Temperature increasing

–

165

–

°C

Thermal Shutdown Hysteresis

TJTSDhys

–15

–

°C

Open LED Detection Threshold

VCE(ODC) IO > 5 mA, VCE ≥ 0.6 V

–

0.30

–

SWITCHING CHARACTERISTICS valid at TA = 25°C, VDD = VIH = 3.0 to 5.5 V, VCE = 0.7 V, VIL = 0 V, REXT = 470 Ω, IO = 40 mA, VLED = 3 V, RLED =

58 Ω, CLED = 10 pF, unless otherwise noted

CLOCK Pulse Width

thigh, tlow

Normal Mode

–

SERIAL DATA IN Setup Time

tSU(D)

–

SERIAL DATA IN Hold Time

tH(D)

–

LATCH ENABLE Setup Time

tSU(LE)

–

LATCH ENABLE Hold Time

tH(LE)

–

OUTPUT ENABLE Set Up Time

tSU(OE)

–

OUTPUT ENABLE Hold Time

tH(OE)

–

OUTPUT ENABLE Pulse Width

tW(OE)

600

–

CLOCK to SERIAL DATA OUT Propagation Delay Time

tP(DO)

–

OUTPUT ENABLE to OUT0 Propagation Delay Time

tP(OE)

–75

–

Staggering Delay (between consecutive outputs)

Total Delay Time (15 × tD)tDtotal

–

300

–

CLOCK Pulse Width

thigh, tlow

Test Mode, VDD = 4.5 to 5.5 V

–

SERIAL DATA IN Setup Time

tSU(D)

–

SERIAL DATA IN Hold Time

tH(D)

–

LATCH ENABLE Setup Time

tSU(LE)

–

LATCH ENABLE Hold Time

tH(LE)

–

OUTPUT ENABLE Set Up Time

tSU(OE)

–

OUTPUT ENABLE Hold Time

tH(OE)

–

OUTPUT ENABLE Pulse Width*

tW(OE)

2.0

–

CLOCK to SERIAL DATA OUT Propagation Delay Time

tP(DO)

–

OUTPUT ENABLE to OUT0 Propagation Delay Time

tP(OE)

–75

–

Staggering Delay (between consecutive outputs)

Total Delay Time (15 × tD)tDtotal

–

300

–

Output Fall Time

90% to 10% voltage

–

150

Output Rise Time

10% to 90% voltage

–

150

*See LED Open Circuit Detection (Test) mode timing diagram.

A6278 Datenblatt(PDF) 4 Page - Allegro MicroSystems

A6278 Datenblatt(HTML) 4 Page - Allegro MicroSystems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datenblatt Download

Link URL