Clamp Duration

Register

Addr

76543210

CL_DUR

04

CLD7

CLD6

CLD5

CLD4

CLD3

CLD2

CLD1

CLD0

This is an 8 bit wide register that sets the width of the active clamp pulse in increments of 2 cycles of the main PLL pixel clock.

Registers 05–07 are not used

Register

Addr

76543210

Not Used

05

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

Not Used

06

RSV

RSV

Not Used

07

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

Registers 05–07 are not used. However, data can be written to these registers and read back from these registers at the “RSV”

locations. Any data written to these registers will not affect the operation of the LM1270.

V Blank Duration

Register

Addr

7

6543210

V_BL_DU

08

VB6

VB5

VB4

VB3

VB2

VB1

VB0

This is a 7 bit wide register that sets the width of the active V Blank pulse in horizontal line periods.

Input A Contrast

Register

Addr

7

6543210

ACONT

09

ABLNK

ACON6

ACON5

ACON4

ACON3

ACON2

ACON1

ACON0

Bit 0–6: This is a 7 bit wide register that sets the contrast level of input A. When the register is zero, the output is at minimum

contrast.

Bit 7:

Setting this bit sets the input A only to black level.

If bit 7 = 0, normal video. (Default)

If bit 7 = 1, Input A set to black level

Input B Contrast

Register

Addr

7

6543210

BCONT

0A

BBLNK

BCON6

BCON5

BCON4

BCON3

BCON2

BCON1

BCON0

Bit 0–6: This is a 7 bit wide register that sets the contrast level of input B. When the register is zero, the output is at minimum

contrast.

Bit 7:

Setting this bit sets the input B only to black level.

If bit 7 = 0, normal video. (Default)

If bit 7 = 1, Input B set to black level

Emphasis

Register

Addr

7

6

5

4

3

2

1

0

EMPHASIS

0B

WIN_SEL

VREF

WCHE

WGHE

RSV

EMP2

EMP1

EMP0

Bit 2–0: This is a 3 bit wide register that sets the emphasis level of input B. When this value is zero, no emphasis is applied.

Bit 3:

Reserved.

Bit 4:

This bit controls the horizontal edge used to start the pixel counters in the Dynamic Window Generation block and Video

Data Transfer detect block.

If bit 4 = 0, H_FEEDBACK which is in sync with PLL, is used for the edge.

If bit 4 = 1, HSYNC synchronized to pixel clock is used as the edge.

Bit 5:

This bit controls the horizontal edge used to start the pixel counters in the Window Calibration block.

If bit 5 = 0, H_FEEDBACK which is in sync with PLL, is used for the edge.

If bit 5 = 1, HSYNC synchronized to pixel clock is used as the edge.

Note: Two separate bits are used in case these blocks need to be in different modes.

Bit 6:

This bit controls which source is selected for the reference voltage V

If bit 6 = 0, internal V

If bit 6 = 1, external V

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