CHRONTEL

CH7035B

4

201-1000-029

Rev. 1.2

06/30/2020

1.2

Pin Description

Table 1: Pin Name Descriptions (QFN88 Package)

Pin #

Type

Symbol

Description

1~6,8,

12~21,

25~29,

87~88,

In

D[23:0]

Data Input

These pins accept 24 data input lines from a digital video port of a

graphics controller. The swing is defined by VDDIO.

All the unused Data input pins should be pulled low with 10K

resistors or shorted to Ground directly.

7

In

RESETB

Reset Input

When this pin is low, the device is held in the power-on reset

condition. When this pin is high, reset is controlled through the serial

port.

31,32

Out

TLC*,TLC

DVI Clock Outputs

These pins provide the differential clock output for the DVI .

34,35

Out

TDC0*,TDC0

DVI Data Channel 0 Outputs

These pins provide the DVI differential outputs for data channel 0

36,37

Out

TDC1*,TDC1

DVI Data Channel 1 Outputs

These pins provide the DVI differential outputs for data channel 1

39,40

Out

TDC2*,TDC2

DVI Data Channel 2 Outputs

These pins provide the DVI differential outputs for data channel 2

43

N/A

Reserved

Reserved

This pin should connect to DVDD directly

44

N/A

Reserved

Reserved

This pin should connect to DGND directly

50

N/A

Reserved

Reserved

This pin should be left open or pulled low with a 10 K resistor in the

application.

51

In

HPD

Hot Plug Detect

This input pin determines whether the DVI output driver is connected

to a DVI monitor. This pin should be pull low with 47 K Resistor.

54

In

SPC

Serial Port Clock Input

This pin functions as the clock pin of the serial port. External pull-up

6.8 K resister is required.

55

In/out

SPD

Serial Port Data Input / Output

This pin functions as the bi-directional data pin of the serial port.

External pull-up 6.8 K resister is required.

56

In

I2S_D/SPDIF

I2S Data input or SPDIF Audio Signal Input

In default, this pin is configured to SPDIF audio signal input. The

signal level is 0-2.5V.

I2S audio input can be configured through programming CH7035B

registers.

57

In

I2S_WS

I2S Channel Select Signal

58

In

I2S_CK

I2S Clock Signal

63

Out

DDC_SC

Routed Serial Port Clock Output to DDC

This pin functions as the clock bus of the serial port to DDC receiver.

This pin will require a pull-up 1.8 K resistor to the desired voltage

level. A pull-low resistor 10 K to ground if unused.

64

In/out

DDC_SD

Routed Serial Port Data to DDC

This pin functions as the bi-directional data pin of the serial port to

DDC receiver. This pin will require a pull-up 1.8 K resistor to the

desired voltage level. A pull-low resistor 10 K to ground if unused

65

In/out

GPIO

General Purpose Input Output

67

Out

XO

Crystal Output

A parallel resonance crystal should be attached between this pin and