ST7293C3B1 datasheet(15/69 Pages) STMICROELECTRONICS

15 / 69 page

15/69

ST7294

3.4.4 PORTC Interrupt

The PORTC Interrupt can be generated on the

falling edge of one of pins PC0-PC5, if it is defined

as an interrupt source. When an enabled interrupt

occurs, normal processing is suspended at the

end of the current instruction execution. It is then

processed according to the flowchart on Figure

11.

If the interrupt is disabled (I high), the triggering

edge of the wake-up interrupt is internally latched

and the interrupt remains pending, to be proc-

essed as soon as the interrupt is enabled. This in-

ternal latch is cleared in the first part of the service

routine. Therefore one, and only one, external in-

terrupt can be latched and serviced at any instant.

3.4.5 Timer Interrupt

Two different timer interrupt flags are capable of

causing a timer interrupt when they are active, if

both the I bit of the CCR is reset, and if the corre-

sponding enable bit is set. If either of these condi-

tions is false, the interrupt is latched and thus re-

mains pending.

The interrupt flags are located in the Timer Status

Control Register (0012h).

When

enabled

interrupt

occurs,

normal

processing is suspended at the end of the current

instruction execution. It is then serviced according

to the flowchart on Figure 11. Software in the Tim-

er Service Routine must determine the priority and

cause of the timer interrupt by examining the inter-

rupt flags and the status bits located in the TSR.

The general sequence for clearing an interrupt is

an access to the status register while the flag is

set followed by a read or write of an associated

the internal latch. A pending interrupt (i.e. waiting

for being enabled) will therefore be lost if the clear

sequence is executed.

Refer to Section 4.3 16-BIT TIMER, for further in-

formation.

INTERRUPTS (Continued)

Table 5. External Interrupt Options

INTP

INTN

External Interrupt Options

Negative edge and low-level sensitive

Negative edge sensitive only

Positive edge sensitive only

Positive and negative edge sensitive

ST7293C3B1 Datenblatt(PDF) 15 Page - STMicroelectronics

ST7293C3B1 Datenblatt(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Datenblatt Download

Link URL