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MPC8540 Datenblatt(PDF) 79 Page - Freescale Semiconductor, Inc

Teilenummer MPC8540
Bauteilbeschribung  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Hersteller  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datenblatt(HTML) 79 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
lxxix
Tables
Table
Number
Title
Page
Number
19-2
PMGC0 Field Descriptions ................................................................................................... 19-5
19-3
PMLCA0 Field Descriptions ................................................................................................ 19-6
19-4
PMLCA1–PMLC8 Field Descriptions.................................................................................. 19-6
19-5
PMLCB0 Field Descriptions................................................................................................. 19-7
19-6
PMLCBn Field Descriptions................................................................................................. 19-8
19-7
PMC0 Field Descriptions.................................................................................................... 19-10
19-8
PMCn Field Descriptions.................................................................................................... 19-10
19-9
Burst Definition................................................................................................................... 19-13
19-10
Performance Monitor Events .............................................................................................. 19-15
19-11
PMGC0 and PMLCAn Settings .......................................................................................... 19-27
19-12
Register Settings for Counting Examples MPC8540.......................................................... 19-28
20-1
POR Configuration Settings and Debug Modes ................................................................... 20-4
20-2
Debug, Watchpoint and Test Signal Summary...................................................................... 20-6
20-3
Debug Signals—Detailed Signal Descriptions ..................................................................... 20-7
20-4
Watchpoint and Trigger Signals—Detailed Signal Descriptions .......................................... 20-8
20-5
JTAG Test and Other Signals—Detailed Signal Descriptions .............................................. 20-9
20-6
Debug and Watchpoint Monitor Memory Map................................................................... 20-10
20-7
WMCR0 Field Descriptions................................................................................................ 20-12
20-8
WMCR1 Field Descriptions................................................................................................ 20-13
20-9
WMAR Field Descriptions ................................................................................................. 20-14
20-10
WMAMR Field Descriptions.............................................................................................. 20-14
20-11
WMTMR Field Descriptions .............................................................................................. 20-15
20-12
Transaction Types by Interface ........................................................................................... 20-15
20-13
WMSR Field Descriptions .................................................................................................. 20-16
20-14
TBCR0 Field Descriptions.................................................................................................. 20-17
20-15
TBCR1 Field Descriptions.................................................................................................. 20-19
20-16
TBAR Field Descriptions.................................................................................................... 20-19
20-17
TBAMR Field Descriptions ................................................................................................ 20-20
20-18
TBTMR Field Descriptions ................................................................................................ 20-21
20-19
TBSR Field Descriptions .................................................................................................... 20-21
20-20
TBACR Field Descriptions ................................................................................................. 20-22
20-21
TBADHR Field Descriptions.............................................................................................. 20-23
20-22
TBADR Field Descriptions................................................................................................. 20-23
20-23
PCIDR Field Descriptions .................................................................................................. 20-24
20-24
CCIDR Field Descriptions .................................................................................................. 20-25
20-25
TOSR Field Descriptions .................................................................................................... 20-26
20-26
Source and Target ID Values ............................................................................................... 20-26
20-27
CMD Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 000) .............................. 20-30
20-28
DDR Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 001) ............................... 20-31
20-29
PCI Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 010) ................................. 20-32



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