AM486DX2 datasheet(37/67 Pages) AMD

37 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

5.4

Pin State During Stop Grant

Table 9 shows the pin states during Stop Grant Bus

states. During the Stop Grant state, most output and

input/output signals of the microprocessor maintain the

level they held when entering the Stop Grant state. The

data and data parity signals are tri-stated. In response

to HOLD being driven active during the Stop Grant state

(when the CLK input is running), the CPU generates

HLDA and tri-states all output and input/output signals

that are tri-stated during the HOLD/HLDA state. After

HOLD is deasserted, all signals return to the same state

they were before the HOLD/HLDA sequence.

To achieve the lowest possible power consumption dur-

ing the Stop Grant state, the system designer must en-

sure that the input signals with pull-up resistors are not

driven Low, and the input signals with pull-down resis-

tors are not driven High.

All inputs except data bus pins must be driven to the

power supply rails to ensure the lowest possible current

consumption during Stop Grant or Stop Clock modes.

For compatibility, data pins must be driven Low to

achieve the lowest possible power consumption.

5.5

Clock Control State Diagram

Figure 20 shows the state transitions during a Stop

Clock cycle.

5.5.1

Normal State

This is the normal operating state of the CPU. While in

the normal state, the CLK input can be dynamically

changed within the specified CLK period stability limits.

5.5.2

Stop Grant State

The Stop Grant state provides a low-power state that

can be entered by simply asserting the external STPCLK

interrupt pin. When the Stop Grant bus cycle has been

placed on the bus, and either RDY or BRDY is returned,

the CPU is in this state. The CPU returns to the normal

execution state 10–20 clock cycles after STPCLK has

been deasserted.

While in the Stop Grant state, the pull-up resistors on

STPCLK and UP are disabled internally. The system

must continue to drive these inputs to the state they

were in immediately before the CPU entered the Stop

Grant State. For minimum CPU power consumption, all

other input pins should be driven to their inactive level

while the CPU is in the Stop Grant state.

Table 9. Pin State During Stop Grant Bus State

Signal

Type

State

A3–A2

Previous State

A31–A4

I/O

Previous State

D31–D0

I/O

Floated

BE3–BE0

Previous State

DP3–DP0

I/O

Floated

W/R, D/C, M/IO, CACHE

Previous State

ADS

Inactive

LOCK, PLOCK

Inactive

BREQ

Previous State

HLDA

As per HOLD

BLAST

Previous State

FERR

Previous State

PCHK

Previous State

SMIACT

Previous State

HITM

Previous State

t20

t21

Figure 19. Entering Stop Grant State

RDY

ADDR

STPCLK

CLK

Stop Grant Bus cycle

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