TLK2521

1 to 2.5 Gbps TRANSCEIVER

SLLS574B − JULY 2003 − REVISED JANUARY 2004

9

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

SIGNAL PIN (CONTINUED)

SYNC

25

Input

(w/pulldown)

Fast synchronization. When asserted high, the transmitter substitute the 18-bit pattern

111111111000000000 ,so that when the start/stop bits are framed around the data the receiver can

immediately detect the proper deserialization boundary. This is typically used during initialization of

the serial link.

PREEMPH

56

Input

Preemphasis. When asserted, the serial transmit outputs have an extra output swing on the first bit

of any run-length of same value bits than when deasserted.

TEST PIN

ENABLE

24

Input

(w/pullup)

Device enable. When this pin is held low, the device is placed in power down mode. When asserted

high while the device is in power-down mode, the transceiver goes into power-on reset before

beginning normal operation.

LOOPEN

21

Input

(w/pulldown)

Loop enable. When LOOPEN is active high, the internal loop−back path is activated. The transmitted

serial data is directly routed internally to the inputs of the receiver. This provides a self-test capability

in conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a

high-impedance state during the loop-back test. LOOPEN is held low during standard operational

state with external serial outputs and inputs active.

LOCKB

26

Output

Receiver lock. When asserted low, it indicates that the receiver has acquired bit synchronization on

the data stream and has located the start/stop bits, so that the deserialized data presented on the

parallel receive bus is properly received.

TESTEN

27

Input

(w/pulldown)

Test mode enable. This pin should be left unconnected or tied low.

POWER PIN

VDD

1, 9,

23, 38,

48

Supply

Digital logic power. Provides power for all digital circuitry and digital I/O buffers.

VDDA

55, 57

Supply

Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and

transmitter.

GROUND PIN

GNDA

52, 58,

61

Ground

Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX.

GND

5, 13,

18, 28,

33, 43

Ground

Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.

−0.3 V to 3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at TXD, ENABLE, GTX_CLK, LOOPEN, SYNC, PREEMPH

−0.3 V to 4 V

. . . . . . . . . . . . . . . . . . .

Voltage range at any other terminal except above

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

See Dissipation Rating Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge

HBM:2 kV, CDM:1.5 kV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Characterized free-air operating temperature range

−40

°C to 85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead Temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground.