LTM8063 datasheet(21/28 Pages) AD

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LTM8080

Rev. 0

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8080 F02

COUT2

COUT1

CSET2

RSET2

RSET1

CBUS

CIN

VSNS1

VOUT1

VSNS2

VOUT2

CSET1

VIN

Figure 2. Layout Showing Suggested External Components, GND

Plane and Thermal Vias

Hot-Plugging Safely

The small size, robustness, and low impedance of ceramic

capacitors make them an attractive option for the input

bypass capacitor of LTM8080. However, these capacitors

can cause problems if the LTM8080 is plugged into a live

supply (Refer ADI Application Note 88 for a complete dis-

cussion). The low-loss ceramic capacitor combined with

stray inductance in series with the power source forms

an underdamped tank circuit, and the voltage at the VIN

pins of the LTM8080 can ring to more than twice the

nominal input voltage, possibly exceeding the LTM8080’s

rating and damaging the part. The input network should

be designed to prevent this overshoot if the input supply is

poorly controlled or the LTM8080 is hot-plugged into an

energized supply. This can be accomplished by installing

a small resistor in series to VIN, but the most popular

method of controlling input voltage overshoot is adding

an electrolytic bulk cap to the VIN net. This capacitor’s rel-

atively high equivalent series resistance damps the circuit

and eliminates the voltage overshoot. The extra capacitor

improves low-frequency ripple filtering and can slightly

improve the efficiency of the circuit, though it is likely to

be the most significant component in the circuit.

Thermal Considerations

The LTM8080 output current may need to be derated if

it is required to operate at a high ambient temperature.

The amount of current derating depends upon the input

voltage, output power, and ambient temperature. The der-

ating curves in the Typical Performance Characteristics

section can be used as a guide. The LTM8080 generated

these curves mounted to a 65.8cm2 4-layer FR4 printed

circuit board. Boards of other sizes and layer counts can

exhibit different thermal behavior, so it is incumbent upon

the user to verify proper operation over the intended sys-

tem’s line, load, and environmental operating conditions.

Many designers use FEA (finite element analysis) to pre-

dict thermal performance for increased accuracy and

fidelity to the actual application. The data sheet typically

gives three thermal coefficients:

1. θJA – Thermal resistance from junction to ambient.

2. θJCbot – Thermal resistance from the junction to the

bottom of the product case.

3. θJCtop – Thermal resistance from junction to the top

of the product case.

While the meaning of each of these coefficients may seem

to be intuitive, JEDEC has defined each to avoid confusion

and inconsistency. These definitions are given in JESD

51-12 and are as follows:

1. θJA is the natural convection junction-to-ambient air

thermal resistance measured in one cubic foot sealed

enclosure. This environment is sometimes referred to

as “still air,” although natural convection causes the

air to move. This value is determined with the part

mounted to a JESD 51-9 defined test board, which

does not reflect an actual application or viable oper-

ating condition.

2. θJCbot is the junction-to-board thermal resistance with

all component power dissipation flowing through the

bottom of the package. In the typical µModule reg-

ulator, the bulk of the heat flows out the bottom of

the package, but there is always heat flow out into

the ambient environment. As a result, this thermal

resistance value may be useful for comparing pack-

ages, but the test conditions don’t generally match

the user’s application.

APPLICATIONS INFORMATION

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