CP548-2N5116

P-Channel JFET Die

Die Size

21 x 21 MILS

Die Thickness

11.5 MILS

Drain Bonding Pad Size

4.0 x 4.0 MILS

Source Bonding Pad Size

4.0 x 4.0 MILS

Gate Bonding Pad Size

4.0 x 4.0 MILS

Top Side Metalization

Al – 30,000Å

Back Side Metalization

Au – 8,000Å

Scribe Alley Width

2.0 MILS

Wafer Diameter

4 INCHES

Gross Die Per Wafer

12,000

The CP548-2N5116 is a silicon P-Channel small signal JFET designed for analog switching

and chopper applications.

MECHANICAL SPECIFICATIONS:

MAXIMUM RATINGS: (TA=25°C)

SYMBOL

UNITS

Gate-Drain Voltage

VGD

30

V

Gate-Source Voltage

VGS

30

V

Gate Current

IG

50

mA

Operating and Storage Junction Temperature

TJ, Tstg

-65 to +150

°C

ELECTRICAL CHARACTERISTICS: (TA=25°C unless otherwise noted)

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

IGSS

VGS=20V

500

pA

IDSS

VDS=15V

5.0

25

mA

ID(OFF)

VDS=15V, VGS=5.0V

500

pA

BVGSS

IG=1.0μA

30

V

VGS(OFF)

VDS=15V, ID=1.0nA

1.0

4.0

V

VGS(f)

IG=1.0mA

1.0

V

VDS(ON)

ID=3.0mA

0.6

V

rDS(ON)

ID=1.0mA, VGS=0

150

Ω

rds(ON)

VGS=0, ID=0, f=1.0kHz

150

Ω

Ciss

VDS=15V, VGS=0, f=1.0MHz

25

pF

Crss

VGS=5.0V, VDS=0, f=1.0MHz

7.0

pF

ton

VDD=6.0V, VGS=5.0V,

42

ns

toff

ID=3.0mA, RL=1.8kΩ

60

ns

R1 (17-January 2018)

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