PFS7628L datasheet(15/38 Pages) POWERINT

15 / 38 page

Rev. F 08/20

PFS7x23-7x29/7633-7636

www.power.com

For high performance designs, use of Litz wire is recommended to

reduce copper loss due to skin effect and proximity effect. For

toroidal inductors the numbers of layers should be less than 3 and for

bobbin wound inductors, inter layer insulation should be used to

minimize inter layer capacitance.

The HiperPFS-4 design spreadsheet simplifies this process and

automatically recommends a core size and design for either ferrite or

Sendust.

Output Diode

For a 385 V nominal PFC output voltage, use of a diode with 600 V or

higher PIV rating is recommended. CCM operation with hard

switching demands that diodes with low reverse recovery time and

reverse recovery charge should be used. The variable frequency

CCM operation of HiperPFS-4 reduces diode switching losses as

compared to fixed frequency solutions and use of readily available

high frequency diodes (such as Qspeed diode family from Power

Integrations), with soft recovery characteristics that result in a

reduced EMI. For highly demanding applications such as 80 PLUS

Gold power supplies, use of Silicon Carbide diodes may be consid-

ered. These uses will typically provide further full load improvement

in efficiency.

Selected diodes should have a forward continuous current rating of at

least 1.2 A to 1.5 A for every 100 W of output power.

Output Capacitor

For a 385 V nominal PFC output voltage, use of an electrolytic

capacitor with 450 V or higher continuous rating is recommended.

The capacitance required is dependent on the acceptable level of

output ripple and any hold up time requirements. The equations

below provide an easy way to determine the required capacitance in

order to meet the hold-up time requirement and also to meet the

output ripple require- ments. The higher of the two values would be

required to be used.

The capacitance required for meeting hold-up time requirements is

calculated using the equation:

PFC output capacitance in farads.

PFC output power in watts.

HOLD-UP

Hold-up time specification for the power supply

in seconds.

OUT

Lowest nominal output voltage of the PFC in volts.

OUT(MIN)

Lowest permissible output voltage of the PFC at

the end of hold-up time in volts.

The capacitance required for meeting the low frequency ripple

specification is calculated using the equation:

Input frequency in Hz.

ΔV

Peak-peak output voltage ripple in volts.

PFC

PFC operating efficiency.

O(MAX)

Maximum output current in amps.

The capacitance calculated using the above method should be

appropriately increased to account for ageing and tolerances.

Power Supply for the IC

A 12 V regulated supply should be used for the HiperPFS-4. If the

VCC exceeds 15 V, the HiperPFS-4 may be damaged. In most

applications a simple series pass linear regulator made using an NPN

transistor and Zener diode is adequate since the HiperPFS-4 only

requires approximately I

CC(ON) maximum for its operation.

It is recommended that a 1 mF or larger, low ESR ceramic capacitor

be used to decouple the VCC supply. This capacitor should be placed

directly at the IC pin on the circuit board.

Line-Sense Network

The line-sense network connected to the VOLTAGE MONITOR pin

provides input voltage information to the HiperPFS-4. A value of 16 MW

is chosen in this example design to minimize power consumption in

these resistors. Only 1% or better tolerance resistors are recommended.

A decoupling capacitor of 470 pF forming an 80 ms time constant is

required to be connected in parallel with the bottom resistor from the

VOLTAGE MONITOR pin to the GROUND pin of the HiperPFS-4. If the

impedance of the resistor divider is different than that shown in the

example schematic, Figure 13, the decoupling capacitor value must

also be changed to maintain the 80 ms time constant. This capacitor

should be placed directly at the IC pin on the circuit board.

Feedback Network

A resistor divider network that provides 3.85 V at the FEEDBACK pin at

the rated output voltage should be used for optimal performance. It

should be scaled in direct proportion to the VOLTAGE MONITOR pin

resistor divider network in order to ensure proper regulation and

power delivery. The HiperPFS-4 controller has been optimized for

operation with an output voltage of 385 VDC. Applications requiring

voltages that deviate from this nominal parameter, thereby requiring

a FEEDBACK pin divider ratio other than the recommended 100:1,

need to be evaluated for trade-offs of the key target parameters of

the specific design. E.g.: the VOLTAGE MONITOR pin divider ratio

should be modified to be equivalent to that of the feedback divider in

order to optimize power factor. However, this will have an impact on

power limit, as well as brown-in/brown-out thresholds, etc. Modifica-

tion of FEEDBACK and VOLTAGE MONITOR pin resistor divider ratios

within 2.5% of nominal should not result in dramatically compromised

performance, but should be thoroughly verified. Changes in excess

of this are not recommended. Itemized trade-offs of this type are

outside the scope of this data sheet.

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