GS815018AB datasheet(13/25 Pages) GSI

13 / 25 page

GS815018/36AB-357/333/300/250

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.05 10/2005

13/25

ZZ Timing

Read A1

Read A2

Deselect

Clock is a Don't care during Sleep ModeRead A1

Read A2

Read A3

KHQX

KHQV

ZZE

KHQX1

ZZR

tKHWX

tWVKH

tKHEX

tEVKH

tKHAX

tAVKH

KLKH

KHKL

KHKH

Begin ISB

SWx

DQn

Note:

K is not shown; assumes K tied to VREF or out of phase with K

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output

drivers are powered by VDDQ.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

GS815018AB Datenblatt(PDF) 13 Page - GSI Technology