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DRA821U2...ALM Datenblatt(PDF) 176 Page - Texas Instruments

Teilenummer DRA821U2...ALM
Bauteilbeschribung  DRA821 Jacinto™ Processors
PDF  252 Pages
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DRA821U2...ALM Datenblatt(HTML) 176 Page - Texas Instruments

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GPMC_FCLK
GPMC_CLK
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_BE1n
GPMC_ADVn_ALE
GPMC_OEn_REn
GPMC_WAIT[j]
Address (MSB)
Valid
Valid
Address (LSB)
Data IN
Data IN
FA0
FA9
FA10
FA3
FA13
FA29
FA1
FA37
FA12
FA4
FA10
FA0
FA5
GPMC_A[27:17]
GPMC_AD[15:0]
GPMC_10
A.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-66. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
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