Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

KSZ9567RTXI-TR Datenblatt(PDF) 136 Page - Microchip Technology

Teilenummer KSZ9567RTXI-TR
Bauteilbeschribung  7-Port Gigabit Ethernet Switch with Audio Video Bridging and Two RGMII/MII/RMII Interfaces
PDF  232 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

KSZ9567RTXI-TR Datenblatt(HTML) 136 Page - Microchip Technology

Back Button KSZ9567RTXI-TR Datasheet HTML 132Page - Microchip Technology KSZ9567RTXI-TR Datasheet HTML 133Page - Microchip Technology KSZ9567RTXI-TR Datasheet HTML 134Page - Microchip Technology KSZ9567RTXI-TR Datasheet HTML 135Page - Microchip Technology KSZ9567RTXI-TR Datasheet HTML 136Page - Microchip Technology KSZ9567RTXI-TR Datasheet HTML 137Page - Microchip Technology KSZ9567RTXI-TR Datasheet HTML 138Page - Microchip Technology KSZ9567RTXI-TR Datasheet HTML 139Page - Microchip Technology KSZ9567RTXI-TR Datasheet HTML 140Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 136 / 232 page
background image
KSZ9567R
DS00002329D-page 136
 2017-2019 Microchip Technology Inc.
5.2.1.5
Port Interrupt Status Register
These registers provide interrupt status for the individual ports. these interrupts are enabled in the Port Interrupt Mask
Register. For non-port specific interrupt status, refer to the Global Interrupt Status Register.
5.2.1.6
Port Interrupt Mask Register
This register enables the interrupts in the Port Interrupt Status Register.
Address:
0xN01B
Port N: 1-7
Size:
8 bits
Bits
Description
Type
Default
7:3
RESERVED
RO
0000_00b
2
PTP Interrupt Status
Applies only to PHY ports, not MAC port(s). Refer to the Port PTP Timestamp
Interrupt Status Register for individual PTP interrupts.
0 = No interrupt
1 = Interrupt detected
RO
0b
1
PHY Interrupt Status
Applies only to PHY ports, not MAC port(s). Refer to the Port Interrupt
Control / Status Register for individual PHY interrupts.
0 = No interrupt
1 = Interrupt detected
RO
0b
0
ACL Interrupt Status
ACL interrupts can be generated by configuring an entry in the ACL Table for
counter mode. All ports have an ACL Table.
To clear this bit, toggle the ACL Interrupt Mask bit in the Port Interrupt Mask
Register.
0 = No interrupt
1 = Interrupt detected
RO
0b
Address:
0xN01F
Port N: 1-7
Size:
8 bits
Bits
Description
Type
Default
7:3
RESERVED
RO
0000_00b
2
PTP Interrupt Enable
Applies only to PHY ports. Refer to the Port PTP Timestamp Interrupt Enable
Register for individual PTP interrupt enables.
0 = Interrupt enabled
1 = Interrupt disabled
R/W
0b
1
PHY Interrupt Enable
Applies only to PHY ports.
0 = Interrupt enabled
1 = Interrupt disabled
R/W
0b



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datenblatt Download

Go To PDF Page


Link URL



War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Link zum Datenblatt    |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com