KSZ9567RTXI-TR datasheet(139/232 Pages) MICROCHIP

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 2017-2019 Microchip Technology Inc.

DS00002329D-page 139

KSZ9567R

5.2.2

PORT N: PORT ETHERNET PHY REGISTERS (0xN100 - 0xN1FF)

The registers in this section are for PHY ports only. Refer to the IEEE802.3 clause 22.3.4 for additional details.

5.2.2.1

PHY Basic Control Register

PHY register 0x00.

Address:

0xN100 - 0xN101

Port N: 1-5

Size:

16 bits

Bits

Description

Type

Default

PHY Software Reset

Set this bit to reset this PHY. Registers are not reset. This bit is self-clearing.

R/W

Local Loopback Mode

Data going from the internal switch fabric to an egress port is looped back at

that egress port and returned to the internal switch fabric.

1 = Local Loopback mode

0 = Normal operation

R/W

Speed Select (LSB)

This bit is ignored if auto-negotiation is enabled (bit 12 in this register).

Bits [6, 13]

11 = Reserved

10 = 1000 Mb/s

01 = 100 Mb/s

00 = 10 Mb/s

R/W

Note 5-4

Auto-Negotiation Enable

1 = Auto-negotiation is enabled

0 = Auto-negotiation is disabled

The initial value of this bit is determined by a strapping option, but it may be

overwritten.

R/W

Note 5-4

Power Down

1 = Power-down mode

0 = Normal operation

When this bit is set to ‘1’, the link-down status might not get updated in the

PHY status register. Software should note link is down and should not rely on

the PHY status register link status.

After this bit is changed from ‘1’ to ‘0’, an internal reset is performed. Wait a

minimum of 1ms before read/write access to this PHY’s registers.

R/W

Isolate

1 = Logical isolation of the PHY from the switch core

0 = Normal operation

R/W

Re-start Auto-Negotiation

Set this bit to re-start auto-negotiation. This bit is self-clearing.

R/W, SC

Duplex Mode

This bit is ignored if auto-negotiation is enabled (bit 12 in this register).

1 = Full duplex

0 = Half duplex

R/W

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