December 1990

2

Philips Semiconductors

Product specification

8-bit parallel-in/serial-out shift register

74HC/HCT166

FEATURES

• Synchronous parallel-to-serial applications

• Synchronous serial data input for easy expansion

• Clock enable for “do nothing” mode

• Asynchronous master reset

• For asynchronous parallel data load see “165”

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT166 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT166 are 8-bit shift registers which have a

fully synchronous serial or parallel data entry selected by

an active LOW parallel enable (PE) input. When PE is

LOW one set-up time prior to the LOW-to-HIGH clock

transition, parallel data is entered into the register. When

each positive-going clock transition.

This feature allows parallel-to-serial converter expansion

stage.

The clock input is a gated-OR structure which allows one

input to be used as an active LOW clock enable (CE) input.

The pin assignment for the CP and CE inputs is arbitrary

and can be reversed for layout convenience. The

LOW-to-HIGH transition of input CE should only take place

while CP is HIGH for predictable operation. A LOW on the

master reset (MR) input overrides all other inputs and

clears the register asynchronously, forcing all bit positions

to a LOW state.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

15

14

20

19

ns

ns

maximum clock frequency

63

50

MHz

input capacitance

3.5

3.5

pF

power dissipation capacitance per package

notes 1 and 2

41

41

pF