74HC181D datasheet(13/20 Pages) PHILIPS

13 / 20 page

1998 Jun 10

Philips Semiconductors

Product speciﬁcation

4-bit arithmetic logic unit

74HC/HCT181

tPHL/ tPLH

propagation

delay

Ai to Fi

4.5

diff

M = S0 =S3 =0V;

S1 =S2 = 4.5 V;

Fig.8; Table 2

tPHL/ tPLH

propagation

delay

Bi to Fi

4.5

diff

M = S0 =S3 =0V;

S1 =S2 = 4.5 V;

Fig.8; Table 2

tPHL/ tPLH

propagation

delay

Ai to Fi

4.5

logic

M = 4.5 V;

Fig.8; Table 3

tPHL/ tPLH

propagation

delay

Bi to Fi

4.5

logic

M = 4.5 V;

Fig.8; Table 3

tPHL/ tPLH

propagation

delay

An to Cn+4

4.5

sum

M = S1 =S2 =0V;

S0 =S3 = 4.5 V;

Fig.8; Table 1

tPHL/ tPLH

propagation

delay

Bn to Cn+4

4.5

sum

M = S1 =S2 =0V;

S0 =S3 = 4.5 V;

Fig.8; Table 1

tPHL/ tPLH

propagation

delay

An to Cn+4

4.5

diff

M = S0 =S3 =0V;

S1 =S2 = 4.5 V;

Fig.10; Table 2

tPHL/ tPLH

propagation

delay

Bn to Cn+4

4.5

diff

M = S0 =S3 =0V;

S1 =S2 = 4.5 V;

Fig.10; Table 2

tPZL/ tPLZ

propagation

delay

An to A=B

4.5

diff

M = S0 =S3 =0V;

S1 =S2 = 4.5 V;

Fig.11; Table 2

tPZL/ tPLZ

propagation

delay

Bn to A=B

4.5

diff

M = S0 =S3 =0V;

S1 =S2 = 4.5 V;

Fig.11; Table 2

tPHL/ tPLH

propagation

delay

An to Fn

4.5

sum

M = S1 =S2 =0V;

S0 =S3 = 4.5 V;

Fig.7; Table 1

tPHL/ tPLH

propagation

delay

Bn to Fn

4.5

sum

M = S1 =S2 =0V;

S0 =S3 = 4.5 V;

Fig.7; Table 1

SYMBOL

PARAMETER

Tamb (°C)

UNIT

TEST CONDITIONS

74HCT

VCC

(V)

MODE OTHER

+25

−40 to +85

−40 to +125

min. typ. max. min.

max.

min.

max.

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